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YosysHQ.yosys/tests/arch
Krystine Sherwin be05fae559 analogdevices: Extra tests
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
2026-01-27 00:25:08 +00:00
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2026-01-27 00:25:08 +00:00
2026-01-27 00:25:08 +00:00
2025-09-23 20:03:50 +02:00