Krystine Sherwin be05fae559 analogdevices: Extra tests ...

`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.

2026-01-27 00:25:08 +00:00

..

memory_attributes

Fixing compiler warning/issues. Moving test script to the correct place

2019-12-16 10:23:45 -06:00

add_sub.v

Unify verilog style

2019-10-18 12:50:24 +02:00

adffs.v

Allow initial blocks to be disabled during tests

2021-11-13 21:53:25 +01:00

blockram.v

analogdevices: Extra tests

2026-01-27 00:25:08 +00:00

blockrom.v

tests: fix blockrom.v driver conflict

2024-12-02 16:56:42 +01:00

counter.v

Fix files with CRLF line endings

2021-06-09 12:16:33 +02:00

dffs.v

Allow initial blocks to be disabled during tests

2021-11-13 21:53:25 +01:00

fsm.v

Fix files with CRLF line endings

2021-06-09 12:16:33 +02:00

latches.v

Unify verilog style

2019-10-18 12:50:24 +02:00

logic.v

Unify verilog style

2019-10-18 12:50:24 +02:00

lutram.v

Rename memory tests to lutram, add more xilinx tests

2019-12-12 17:44:37 -08:00

mul.v

intel_alm: Add multiply signedness to cells

2020-08-26 22:50:16 +02:00

mux.v

Unify verilog style

2019-10-18 12:50:24 +02:00

shifter.v

Allow initial blocks to be disabled during tests

2021-11-13 21:53:25 +01:00

tribuf.v

Unify verilog style

2019-10-18 12:50:24 +02:00