github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-22 10:41:43 +00:00
Code Issues Releases Wiki Activity
YosysHQ.yosys/tests/various
History
Jannis Harder 9288107f43 Test flatten and opt_clean's $scopeinfo handling
2024-02-06 17:51:29 +01:00
..
dynamic_part_select
Add torture test for (* nowrshmsk *) stride optimization
2024-01-10 20:28:36 +01:00
.gitignore
don't use sed -i because it won't work on macos
2022-06-03 01:09:57 -07:00
abc9.v
…
abc9.ys
abc9: uniquify blackboxes like whiteboxes (#2695)
2021-03-29 22:02:06 -07:00
aiger_dff.ys
write_aiger: Fix non-$_FF_ FFs
2022-08-18 13:56:22 +02:00
async.sh
tests: use /usr/bin/env for bash.
2023-08-12 11:59:39 +10:00
async.v
…
attrib05_port_conn.v
…
attrib05_port_conn.ys
…
attrib07_func_call.v
tests: fix some test warnings
2020-05-25 10:07:58 -07:00
attrib07_func_call.ys
…
autoname.ys
…
blackbox_wb.ys
blackbox: Include whiteboxed modules
2021-03-17 13:58:04 +00:00
bug1496.ys
…
bug1531.ys
…
bug1614.ys
…
bug1710.ys
ast: fixes #1710; do not generate RTLIL for unreachable ternary
2020-02-27 16:55:55 -08:00
bug1745.ys
Add regression tests for new handling of comments in constants
2020-03-14 11:41:09 +01:00
bug1781.ys
fsm_extract: Initialize celltypes with full design.
2020-03-19 18:51:21 +01:00
bug1876.ys
tests: add testcases from #1876
2020-04-14 12:39:10 -07:00
bug2014.ys
test: add test for #2014
2020-05-02 14:22:37 -07:00
bug3462.ys
Add test for bug 3462
2022-08-29 10:10:09 +02:00
bug4082.ys
rtlil: Add wire deletion test
2024-01-29 11:25:54 +01:00
cellarray_array_connections.ys
simplify: regression test for AST_CELLARRAY simplification issue
2022-12-07 18:41:55 +01:00
chformal_check.ys
Additional tests for FV $check compatibility
2024-02-02 16:07:10 +01:00
chformal_coverenable.ys
Additional tests for FV $check compatibility
2024-02-02 16:07:10 +01:00
chparam.sh
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
clk2fflogic_effects.sh
Additional tests for FV $check compatibility
2024-02-02 16:07:10 +01:00
clk2fflogic_effects.sv
Additional tests for FV $check compatibility
2024-02-02 16:07:10 +01:00
const_arg_loop.sv
verilog: fix sizing of constant args for tasks/functions
2021-02-21 15:44:43 -05:00
const_arg_loop.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
const_func_block_var.v
Allow localparams in constant functions
2020-08-20 20:10:24 -04:00
const_func_block_var.ys
Allow blocks with declarations within constant functions
2020-07-25 10:16:12 -06:00
const_func.sv
verilog: fix sizing of constant args for tasks/functions
2021-02-21 15:44:43 -05:00
const_func.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
constant_drive_conflict.ys
check: Also check for conflicts with constant drivers
2023-06-23 18:07:28 +02:00
constcomment.ys
Add regression tests for new handling of comments in constants
2020-03-14 11:41:09 +01:00
constmsk_test.v
…
constmsk_test.ys
…
constmsk_testmap.v
tests: fix some test warnings
2020-05-25 10:07:58 -07:00
countbits.sv
Add tests for $countbits
2021-02-26 12:28:58 -05:00
countbits.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
deminout_unused.ys
deminout: Don't demote inouts with unused bits
2020-03-04 18:44:38 +00:00
design1.ys
design: add test
2020-04-16 12:48:40 -07:00
design2.ys
tests: add design -delete tests
2020-04-16 08:05:18 -07:00
design.ys
design: add test
2020-04-16 12:48:40 -07:00
dynamic_part_select.ys
Add torture test for (* nowrshmsk *) stride optimization
2024-01-10 20:28:36 +01:00
elab_sys_tasks.sv
…
elab_sys_tasks.ys
…
equiv_make_make_assert.ys
equiv_make: Add -make_assert option
2022-06-24 00:17:02 +01:00
equiv_opt_multiclock.ys
…
equiv_opt_undef.ys
equiv_induct: Fix up assumption for $equiv cells in -undef mode.
2020-07-27 18:36:13 +02:00
exec.ys
Add test for exec command.
2020-03-16 07:52:58 +00:00
fib_tern.v
verilog: support recursive functions using ternary expressions
2021-02-12 14:43:42 -05:00
fib_tern.ys
verilog: support recursive functions using ternary expressions
2021-02-12 14:43:42 -05:00
fib.v
verilog: improved support for recursive functions
2020-12-31 18:33:59 -07:00
fib.ys
verilog: improved support for recursive functions
2020-12-31 18:33:59 -07:00
func_port_implied_dir.sv
sv: complete support for implied task/function port directions
2020-12-31 16:17:13 -07:00
func_port_implied_dir.ys
sv: complete support for implied task/function port directions
2020-12-31 16:17:13 -07:00
gen_if_null.v
verilog: significant block scoping improvements
2021-01-31 09:42:09 -05:00
gen_if_null.ys
verilog: significant block scoping improvements
2021-01-31 09:42:09 -05:00
global_scope.ys
ast: Fix handling of identifiers in the global scope
2020-04-16 10:30:07 +01:00
gzip_verilog.v.gz
…
gzip_verilog.ys
…
help.ys
tests: Fix invocation of 'help -cells'
2023-07-10 12:42:09 +02:00
hierarchy_defer.ys
…
hierarchy_param.ys
hierarchy: Convert positional parameters to named.
2020-04-21 19:09:00 +02:00
hierarchy.sh
…
ice40_mince_abc9.ys
Add test for abc9+mince issue
2020-03-20 20:35:28 +00:00
integer_range_bad_syntax.ys
Revert "Revert PRs #2203 and #2244."
2020-07-10 09:59:48 +02:00
integer_real_bad_syntax.ys
Revert "Revert PRs #2203 and #2244."
2020-07-10 09:59:48 +02:00
json_escape_chars.ys
fix handling of escaped chars in json backend and frontend
2022-02-18 17:13:09 +01:00
logger_error.ys
Added back tests for logger
2020-03-13 15:00:18 +01:00
logger_fail.sh
tests: use /usr/bin/env for bash.
2023-08-12 11:59:39 +10:00
logger_nowarning.ys
Added back tests for logger
2020-03-13 15:00:18 +01:00
logger_warn.ys
Added back tests for logger
2020-03-13 15:00:18 +01:00
logger_warning.ys
Added back tests for logger
2020-03-13 15:00:18 +01:00
logic_param_simple.ys
Revert "Revert PRs #2203 and #2244."
2020-07-10 09:59:48 +02:00
mem2reg.ys
…
memory_word_as_index.data
Fix elaboration of whole memory words used as indices
2020-12-26 21:47:38 -07:00
memory_word_as_index.v
Fix elaboration of whole memory words used as indices
2020-12-26 21:47:38 -07:00
memory_word_as_index.ys
Fix elaboration of whole memory words used as indices
2020-12-26 21:47:38 -07:00
muxcover.ys
muxcover: do not add decode muxes with x inputs
2023-01-26 05:19:45 +00:00
muxpack.v
More deadname stuff
2021-06-09 12:40:33 +02:00
muxpack.ys
More deadname stuff
2021-06-09 12:40:33 +02:00
param_struct.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
peepopt.ys
peepopt: Fix padding for the peepopt_shiftmul_right pattern
2023-12-06 18:35:44 +01:00
plugin.cc
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
plugin.sh
tests: use yosys-config --datdir instead of hard-coded
2020-04-22 08:29:45 -07:00
pmgen_reduce.ys
…
pmux2shiftx.v
…
pmux2shiftx.ys
…
port_sign_extend.v
genrtlil: fix signed port connection codegen failures
2021-02-05 19:51:30 -05:00
port_sign_extend.ys
genrtlil: fix signed port connection codegen failures
2021-02-05 19:51:30 -05:00
primitives.ys
tests: add tests for primitives' src
2020-05-04 10:21:47 -07:00
printattr.ys
printattrs: Add test.
2020-05-27 08:00:00 +00:00
rand_const.sv
Allow combination of rand and const modifiers
2021-01-21 08:42:05 -07:00
rand_const.ys
Allow combination of rand and const modifiers
2021-01-21 08:42:05 -07:00
reg_wire_error.sv
…
reg_wire_error.ys
…
rename_scramble_name.ys
rename: add -scramble-name option to randomly rename selections
2022-08-08 16:03:28 +01:00
rtlil_z_bits.ys
backends/rtlil: Do not shorten a value with z bits to 'x
2023-01-29 14:02:25 +01:00
run-test.sh
tests: Centralize test collection and Makefile generation
2020-09-21 15:07:02 +02:00
scopeinfo.ys
Test flatten and opt_clean's $scopeinfo handling
2024-02-06 17:51:29 +01:00
scratchpad.ys
…
script.ys
…
sformatf.ys
ast: use new format string helpers.
2023-08-11 04:46:52 +02:00
shregmap.v
tests: fix some test warnings
2020-05-25 10:07:58 -07:00
shregmap.ys
…
signed.ys
Revert "Revert PRs #2203 and #2244."
2020-07-10 09:59:48 +02:00
signext.ys
…
sim_const.ys
sim: Fix handling of constant-connected cell inputs at startup
2020-04-21 08:58:52 +01:00
specify.v
…
specify.ys
verilog: fix specify src attribute
2020-05-04 10:53:06 -07:00
src.ys
verilog: add test
2020-03-11 06:51:03 -07:00
sta.ys
sta: very crude static timing analysis pass
2021-11-25 17:20:27 +01:00
struct_access.sv
Fix access to whole sub-structs (#3086)
2022-02-14 14:34:20 +01:00
struct_access.ys
tests: Run async2sync before sat and/or sim to handle $check cells
2024-02-01 16:14:11 +01:00
sub.v
Add test for bug 3462
2022-08-29 10:10:09 +02:00
submod_extract.ys
…
submod.ys
…
sv_defines_dup.ys
Add support for SystemVerilog-style `define to Verilog frontend
2020-03-27 16:08:26 +00:00
sv_defines_mismatch.ys
Add support for SystemVerilog-style `define to Verilog frontend
2020-03-27 16:08:26 +00:00
sv_defines_too_few.ys
Add support for SystemVerilog-style `define to Verilog frontend
2020-03-27 16:08:26 +00:00
sv_defines.ys
Add support for SystemVerilog-style `define to Verilog frontend
2020-03-27 16:08:26 +00:00
sv_implicit_ports.sh
tests: use /usr/bin/env for bash.
2023-08-12 11:59:39 +10:00
svalways.sh
tests: use /usr/bin/env for bash.
2023-08-12 11:59:39 +10:00
wreduce.ys
…
write_gzip.ys
…
xaiger.ys
xaiger: add testcase
2020-05-24 08:48:23 -07:00