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YosysHQ.yosys/frontends/ast/simplify.cc
Clifford Wolf 3d27c1cc80 Merge pull request #513 from udif/pr_reg_wire_error
Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
2018-08-15 13:35:41 +02:00

128 KiB