Emil J. Tywoniak dcd73b6b03 verilog_backend: alter only design copy unless -wreck

2026-01-21 14:48:32 +01:00

..

aiger

Remove .c_str() calls from log()/log_error()

2025-09-11 20:59:37 +00:00

aiger2

aiger2: fix case where submodule cell input port has empty SigSpec

2025-12-01 19:40:58 +01:00

blif

Remove .c_str() calls from log()/log_error()

2025-09-11 20:59:37 +00:00

btor

write_btor: Include $assert and $assume cells in -ywmap output

2025-10-09 14:50:36 +02:00

cxxrtl

Pass IdString by value instead of by const reference.

2025-12-22 01:52:59 +00:00

edif

Remove unnecessary .c_str() in EDIF_ macros

2025-09-16 23:14:11 +00:00

firrtl

Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix()

2025-09-16 23:02:16 +00:00

functional

Fixes

2025-12-02 11:17:21 -08:00

intersynth

Remove .c_str() calls from log()/log_error()

2025-09-11 20:59:37 +00:00

jny

Remove .c_str() calls from log()/log_error()

2025-09-11 20:59:37 +00:00

json

Remove .c_str() calls from log()/log_error()

2025-09-11 20:59:37 +00:00

rtlil

Merge pull request #5473 from YosysHQ/krys/unsized_params

2025-11-12 07:14:44 +13:00

simplec

Update backends to avoid bits()

2025-09-16 03:17:23 +00:00

smt2

Deliver more helpful error messages

2026-01-06 16:19:54 -08:00

smv

Remove .c_str() calls from log()/log_error()

2025-09-11 20:59:37 +00:00

spice

Remove .c_str() calls from log()/log_error()

2025-09-11 20:59:37 +00:00

table

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

verilog

verilog_backend: alter only design copy unless -wreck

2026-01-21 14:48:32 +01:00