github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-23 02:58:29 +00:00
Code Issues Releases Wiki Activity
YosysHQ.yosys/docs/source/using_yosys
History
Gary Wong 4ffd05af6f verilog: add support for SystemVerilog string literals. 
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-08-11 13:34:10 +02:00
..
more_scripting
Docs: Fix cmd links from bugpoint docs
2025-08-06 13:52:13 +12:00
synthesis
Reapply "Add groups to command reference"
2025-08-06 13:52:12 +12:00
bugpoint.rst
Docs: Fix cmd links from bugpoint docs
2025-08-06 13:52:13 +12:00
index.rst
Docs: Move verilog.rst to using_yosys
2025-08-05 09:53:58 +12:00
verilog.rst
verilog: add support for SystemVerilog string literals.
2025-08-11 13:34:10 +02:00