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verilog BLT
This commit is contained in:
aap
parent
f926fd9098
commit
844810b249
@ -335,8 +335,8 @@ module apr(
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wire ft6;
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wire ft6a;
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wire ft7;
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wire f_c_c_aclt = jp_pop | jp_popj;
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wire f_c_c_acrt = jp_jra | ir_blt;
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wire f_c_c_aclt = jp_jra | ir_blt;
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wire f_c_c_acrt = jp_pop | jp_popj;
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wire f_ac_2 = sh_ac_2 | ir_md_f_ac_2;
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wire f_c_c_aclt_OR_rt = f_c_c_aclt | f_c_c_acrt;
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wire f_ac_2_etc = f_c_c_aclt_OR_rt | f_ac_2;
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@ -1458,7 +1458,9 @@ module apr(
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wire cfac_ar_add = 0;
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wire cfac_ar_sub = 0;
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wire cfac_mb_fm_mqJ = 0;
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wire cfac_mb_mq_swap = 0;
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wire cfac_mb_mq_swap = dst2 | dst3 | dst7 |
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dst9 | dst19a | dst21a |
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blt_t0 | blt_t3a | blt_t5;
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wire cfac_mb_ar_swap = 0;
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wire cfac_ar_com = 0;
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wire cfac_overflow = 0;
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@ -1477,25 +1479,90 @@ module apr(
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reg blt_f0a;
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reg blt_f3a;
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reg blt_f5a;
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wire blt_done = 0;
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wire blt_last = 0;
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wire blt_done = ~mq[0] | pi_rq;
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wire blt_last = ir_blt & ~mq[0];
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wire blt_t0 = 0;
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wire blt_t0a = 0;
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wire blt_t1 = 0;
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wire blt_t2 = 0;
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wire blt_t3 = 0;
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wire blt_t3a = 0;
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wire blt_t4 = 0;
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wire blt_t5 = 0;
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wire blt_t5a = 0;
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wire blt_t6 = 0;
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wire blt_t0;
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wire blt_t0a;
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wire blt_t1;
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wire blt_t2;
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wire blt_t3;
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wire blt_t3a;
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wire blt_t4;
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wire blt_t5;
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wire blt_t5a;
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wire blt_t6;
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wire blt_t6_D;
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pa blt_pa0(.clk(clk), .reset(reset),
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.in(et3 & ir_blt),
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.p(blt_t0));
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pa blt_pa1(.clk(clk), .reset(reset),
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.in(mc_rs_t1 & blt_f0a),
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.p(blt_t0a));
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pa blt_pa2(.clk(clk), .reset(reset),
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.in(blt_t0a_D),
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.p(blt_t1));
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pa blt_pa3(.clk(clk), .reset(reset),
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.in(blt_t1_D),
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.p(blt_t2));
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pa blt_pa4(.clk(clk), .reset(reset),
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.in(blt_t2_D),
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.p(blt_t3));
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pa blt_pa5(.clk(clk), .reset(reset),
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.in(ar_t3 & blt_f3a),
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.p(blt_t3a));
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pa blt_pa6(.clk(clk), .reset(reset),
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.in(blt_t3a_D),
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.p(blt_t4));
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pa blt_pa7(.clk(clk), .reset(reset),
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.in(blt_t4_D),
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.p(blt_t5));
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pa blt_pa8(.clk(clk), .reset(reset),
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.in(ar_t3 & blt_f5a),
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.p(blt_t5a));
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pa blt_pa9(.clk(clk), .reset(reset),
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.in(blt_t5a & ~blt_done),
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.p(blt_t6));
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wire blt_t0a_D, blt_t1_D;
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wire blt_t2_D, blt_t3a_D;
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wire blt_t4_D, blt_t6_D;
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dly100ns blt_dly0(.clk(clk), .reset(reset),
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.in(blt_t0a),
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.p(blt_t0a_D));
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dly100ns blt_dly1(.clk(clk), .reset(reset),
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.in(blt_t1),
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.p(blt_t1_D));
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dly100ns blt_dly2(.clk(clk), .reset(reset),
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.in(blt_t2),
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.p(blt_t2_D));
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dly100ns blt_dly3(.clk(clk), .reset(reset),
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.in(blt_t3a),
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.p(blt_t3a_D));
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dly100ns blt_dly4(.clk(clk), .reset(reset),
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.in(blt_t4),
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.p(blt_t4_D));
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dly100ns blt_dly5(.clk(clk), .reset(reset),
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.in(blt_t6),
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.p(blt_t6_D));
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always @(posedge clk) begin
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if(mr_clr | blt_t0a)
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blt_f0a <= 0;
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if(blt_t0)
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blt_f0a <= 1;
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if(mr_clr | blt_t3a)
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blt_f3a <= 0;
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if(blt_t3)
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blt_f3a <= 1;
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if(mr_clr | blt_t5a)
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blt_f5a <= 0;
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if(blt_t5)
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blt_f5a <= 1;
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end
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/*
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* FS
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*/
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@ -76,7 +76,7 @@ module core161c(
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reg cmc_pse_sync;
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reg cmc_stop;
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reg [0:36] core[0:040000];
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reg [0:35] core[0:040000];
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wire cyc_rq_p0 = memsel_p0 == membus_sel_p0 &
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~membus_fmc_select_p0 & membus_rq_cyc_p0;
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@ -1,18 +1,18 @@
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[*]
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[*] GTKWave Analyzer v3.3.76 (w)1999-2016 BSI
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[*] Mon Nov 21 10:43:37 2016
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[*] Thu Nov 24 10:04:34 2016
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[*]
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[dumpfile] "/home/aap/src/pdp6/verilog/dump.vcd"
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[dumpfile_mtime] "Mon Nov 21 10:38:44 2016"
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[dumpfile_size] 250577
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[dumpfile_mtime] "Thu Nov 24 09:54:12 2016"
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[dumpfile_size] 223600
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[savefile] "/home/aap/src/pdp6/verilog/test.gtkw"
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[timestart] 4906
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[timestart] 4587
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[size] 1920 1080
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[pos] -1 -1
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*-7.734977 5505 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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*-10.555068 11855 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] test.
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[treeopen] test.pdp6.
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[treeopen] test.pdp6.mem0.
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[treeopen] test.pdp6.fmem0.
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[sst_width] 337
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[signals_width] 442
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[sst_expanded] 1
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@ -181,6 +181,9 @@ test.pdp6.apr0.f_c_c_aclt
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test.pdp6.apr0.f_c_c_acrt
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test.pdp6.apr0.f_ac_2
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test.pdp6.apr0.f_ac_2_etc
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@200
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-
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@28
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test.pdp6.apr0.ft0
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test.pdp6.apr0.ft1
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test.pdp6.apr0.f1a
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@ -203,7 +206,9 @@ test.pdp6.apr0.et0a
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test.pdp6.apr0.et0
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test.pdp6.apr0.et1
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test.pdp6.apr0.et3
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test.pdp6.apr0.et4_inh
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test.pdp6.apr0.et4
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test.pdp6.apr0.et5_inh
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test.pdp6.apr0.et5
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test.pdp6.apr0.et6
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test.pdp6.apr0.et7
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@ -212,12 +217,14 @@ test.pdp6.apr0.et9
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test.pdp6.apr0.et10
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@1401200
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-E
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@c00200
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@800200
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-S
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@28
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test.pdp6.apr0.s_ac_0
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test.pdp6.apr0.s_ac_2
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@29
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test.pdp6.apr0.s_ac_inh
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@28
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test.pdp6.apr0.s_ac_inh_if_ac_0
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test.pdp6.apr0.st1
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test.pdp6.apr0.st2
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@ -229,7 +236,7 @@ test.pdp6.apr0.st5a
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test.pdp6.apr0.st6
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test.pdp6.apr0.sf7
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test.pdp6.apr0.st7
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@1401200
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@1000200
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-S
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@c00200
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-iobus
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@ -271,6 +278,49 @@ test.pdp6.apr0.mc_non_exist_mem_rst
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test.pdp6.apr0.mc_non_exist_rd
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@1401200
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-membus
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@c00030
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test.fmem0scope[0:35]
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@28
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(0)test.fmem0scope[0:35]
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(1)test.fmem0scope[0:35]
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(2)test.fmem0scope[0:35]
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(3)test.fmem0scope[0:35]
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(4)test.fmem0scope[0:35]
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(5)test.fmem0scope[0:35]
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(6)test.fmem0scope[0:35]
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(7)test.fmem0scope[0:35]
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(8)test.fmem0scope[0:35]
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(9)test.fmem0scope[0:35]
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(10)test.fmem0scope[0:35]
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(11)test.fmem0scope[0:35]
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(12)test.fmem0scope[0:35]
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(13)test.fmem0scope[0:35]
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(14)test.fmem0scope[0:35]
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(15)test.fmem0scope[0:35]
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(16)test.fmem0scope[0:35]
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(17)test.fmem0scope[0:35]
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(18)test.fmem0scope[0:35]
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(19)test.fmem0scope[0:35]
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(20)test.fmem0scope[0:35]
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(21)test.fmem0scope[0:35]
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(22)test.fmem0scope[0:35]
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(23)test.fmem0scope[0:35]
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(24)test.fmem0scope[0:35]
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(25)test.fmem0scope[0:35]
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(26)test.fmem0scope[0:35]
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(27)test.fmem0scope[0:35]
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(28)test.fmem0scope[0:35]
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(29)test.fmem0scope[0:35]
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(30)test.fmem0scope[0:35]
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(31)test.fmem0scope[0:35]
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(32)test.fmem0scope[0:35]
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(33)test.fmem0scope[0:35]
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(34)test.fmem0scope[0:35]
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(35)test.fmem0scope[0:35]
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@1401200
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-group_end
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@30
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test.mem0scope[0:35]
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@c00200
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-mem0
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@28
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@ -332,6 +382,21 @@ test.pdp6.mem0.cmc_t11
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test.pdp6.mem0.cmc_t12
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@1401200
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-mem0
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@c00200
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-fmem0
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@28
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test.pdp6.fmem0.fma_rd_rq
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test.pdp6.fmem0.fma_wr_rq
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@200
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-
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@28
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test.pdp6.fmem0.fmct0
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test.pdp6.fmem0.fmct1
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test.pdp6.fmem0.fmct3
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test.pdp6.fmem0.fmct4
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test.pdp6.fmem0.fmct5
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@1401200
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-fmem0
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@28
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test.pdp6.apr0.at1_inh
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test.pdp6.apr0.ia_NOT_int
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@ -439,13 +504,12 @@ test.pdp6.apr0.iobus_pi_req[1:7]
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test.pdp6.apr0.cpa_req[1:7]
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@1401200
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-cpa
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@800200
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@c00200
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-shift
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@28
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test.pdp6.apr0.sht0
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test.pdp6.apr0.sht1
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test.pdp6.apr0.shf1
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@29
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test.pdp6.apr0.sht1a
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@200
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-
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@ -453,7 +517,27 @@ test.pdp6.apr0.sht1a
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test.pdp6.apr0.sct0
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test.pdp6.apr0.sct1
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test.pdp6.apr0.sct2
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@1000200
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@1401200
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-shift
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@800200
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-BLT
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@28
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test.pdp6.apr0.blt_last
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test.pdp6.apr0.blt_done
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test.pdp6.apr0.blt_t0
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test.pdp6.apr0.blt_f0a
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test.pdp6.apr0.blt_t0a
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test.pdp6.apr0.blt_t1
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test.pdp6.apr0.blt_t2
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test.pdp6.apr0.blt_t3
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test.pdp6.apr0.blt_f3a
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test.pdp6.apr0.blt_t3a
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test.pdp6.apr0.blt_t4
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test.pdp6.apr0.blt_t5
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test.pdp6.apr0.blt_f5a
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test.pdp6.apr0.blt_t5a
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test.pdp6.apr0.blt_t6
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@1000200
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-BLT
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[pattern_trace] 1
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[pattern_trace] 0
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@ -26,7 +26,7 @@ module test;
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initial begin
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stop = 0;
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// #110000 stop = 1;
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#20000 stop = 1;
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#50000 stop = 1;
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end
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always @(pdp6.apr0.st7)
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if(pdp6.apr0.st7)
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@ -36,11 +36,11 @@ module test;
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always @(stop)
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if(stop) begin: fin
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integer i;
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for(i = 0; i < 'o50; i = i + 1)
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if(i < 'o20)
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$display("%o %o %o", i, pdp6.mem0.core[i], pdp6.fmem0.ff[i]);
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else
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$display("%o %o", i, pdp6.mem0.core[i]);
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#1000;
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for(i = 0; i < 'o20; i = i + 1)
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$display("%o %o %o", i, pdp6.mem0.core[i], pdp6.fmem0.ff[i]);
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for(i = 'o1000; i < 'o1010; i = i + 1)
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$display("%o %o", i, pdp6.mem0.core[i]);
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$finish;
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end
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@ -155,12 +155,18 @@ module test;
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end
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*/
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initial begin
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initial begin: meminit
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integer i;
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#1 reset = 1;
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#20 reset = 0;
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pdp6.datasw = 36'o111777222666;
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pdp6.mas = 18'o000030;
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pdp6.mas = 18'o000060;
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for(i = 0; i < 'o40000; i = i + 1)
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pdp6.mem0.core[i] = 0;
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for(i = 0; i < 'o20; i = i + 1)
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pdp6.fmem0.ff[i] = 0;
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pdp6.fmem0.ff['o0] = 36'o000000_010000;
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pdp6.fmem0.ff['o1] = 36'o000000_010222;
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@ -169,7 +175,8 @@ module test;
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pdp6.fmem0.ff['o4] = 36'o000000_010304;
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pdp6.fmem0.ff['o5] = 36'o377777_777777;
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pdp6.fmem0.ff['o6] = 36'o444000_222000;
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pdp6.fmem0.ff['o7] = 36'o777776_000010;
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pdp6.fmem0.ff['o7] = 36'o777776_000010; // BLK ptr
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pdp6.fmem0.ff['o10] = 36'o000002_001000; // BLT ptr
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pdp6.fmem0.ff['o17] = 36'o777000_001000; // PDL ptr
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// pdp6.fmem0.ff['o17] = 36'o777000_777777; // PDL ptr
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pdp6.mem0.core['o20] = 36'o200_064_000104; // MOVE 1,@104(4) FAC_INH
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@ -192,9 +199,14 @@ module test;
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pdp6.mem0.core['o55] = 36'o245_100_777775; // ROTC 2,-3
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pdp6.mem0.core['o56] = 36'o244_100_000001; // ASHC 2,1
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pdp6.mem0.core['o60] = 36'o251_400_001001; // BLT 10,1007
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pdp6.mem0.core['o10410] = 36'o000_000_000333;
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end
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wire [0:35] mem0scope = pdp6.mem0.core['o1000];
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wire [0:35] fmem0scope = pdp6.fmem0.ff[2];
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initial begin
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#25 pdp6.sw_power = 1;
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end
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