mirror of
https://github.com/aap/pdp6.git
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finished implementing character operations
This commit is contained in:
aap
parent
55063c54fd
commit
94436d621a
70
apr.c
70
apr.c
@ -455,6 +455,8 @@ pulse(sht1a);
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pulse(cht3);
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pulse(cht3a);
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pulse(cht8a);
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pulse(lct0a);
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pulse(dct0a);
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pulse(pir_stb);
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// TODO: find A LONG, it probably doesn't exist
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@ -498,6 +500,7 @@ pulse(mp_clr){
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apr->chf4 = 0;
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apr->chf5 = 0;
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apr->chf6 = 0;
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apr->lcf1 = 0; // 6-20
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apr->shf1 = 0; // 6-20
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}
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@ -544,6 +547,7 @@ pulse(mr_clr){
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apr->blt_f3a = 0; // 6-18
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apr->blt_f5a = 0; // 6-18
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apr->uuo_f1 = 0; // 5-10
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apr->dcf1 = 0; // 6-20
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// EX UUO SYNC
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decodeir(apr);
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@ -870,6 +874,8 @@ pulse(sct2){
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trace("SCT2\n");
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if(apr->shf1) nextpulse(apr, sht1a); // 6-20
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if(apr->chf4) nextpulse(apr, cht8a); // 6-19
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if(apr->lcf1) nextpulse(apr, lct0a); // 6-20
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if(apr->dcf1) nextpulse(apr, dct0a); // 6-20
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}
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pulse(sct1){
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@ -938,6 +944,13 @@ pulse(sct1){
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}
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if(apr->chf4)
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MQ_SH_LT;
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if(apr->lcf1)
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AR_SH_RT;
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if(apr->dcf1){
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AR_SH_LT;
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MQ_SH_LT;
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}
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if(!(apr->mb & F18) && (apr->inst == ASH || apr->inst == ASHC) && AR0_XOR_AR1){
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apr->ar_ov_flag = 1; // 6-10
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recalc_cpa_req(apr);
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@ -1007,11 +1020,64 @@ pulse(sht0){
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* Character subroutines
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*/
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pulse(dct3){
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trace("DCT3\n");
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apr->mb &= apr->ar; // 6-3
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apr->chf7 = 0; // 6-19
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nextpulse(apr, et10); // 5-5
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}
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pulse(dct2){
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trace("DCT2\n");
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apr->ar = ~apr->ar & FW; // 6-17
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nextpulse(apr, dct3); // 6-20
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}
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pulse(dct1){
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trace("DCT1\n");
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apr->ar &= apr->mb; // 6-8
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apr->mb = apr->mq; // 6-17
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nextpulse(apr, dct2); // 6-20
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}
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pulse(dct0a){
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trace("DCT0A\n");
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apr->dcf1 = 0; // 6-20
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swap(&apr->mb, &apr->mq); // 6-17, 6-13 (dct0b)
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apr->ar = ~apr->ar & FW; // 6-17
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nextpulse(apr, dct1); // 6-20
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}
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pulse(dct0){
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trace("DCT0\n");
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apr->dcf1 = 1; // 6-20
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SC_COM; // 6-15
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nextpulse(apr, sct0); // 6-16
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}
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pulse(lct0a){
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trace("LCT0A\n");
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apr->lcf1 = 0; // 6-20
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apr->ar &= apr->mb; // 6-8
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apr->chf7 = 0; // 6-19
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nextpulse(apr, et10); // 5-5
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}
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pulse(lct0){
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trace("LCT0\n");
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apr->ar = apr->mb; // 6-8
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apr->mb = apr->mq; // 6-17
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SC_COM; // 6-15
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apr->lcf1 = 1; // 6-20
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nextpulse(apr, sct0); // 6-16
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}
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pulse(cht9){
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trace("CHT9\n");
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apr->sc = apr->fe; // 6-15
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apr->chf5 = 1; // 6-19
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apr->chf7 = 1; // 6-19
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nextpulse(apr, at0); // 5-3
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}
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pulse(cht8a){
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@ -1593,6 +1659,10 @@ pulse(et0){
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nextpulse(apr, cht1); // 6-19
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if(CH_N_INC_OP)
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nextpulse(apr, cht6); // 6-19
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if(CH_LOAD)
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nextpulse(apr, lct0); // 6-20
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if(CH_DEP)
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nextpulse(apr, dct0); // 6-20
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// TODO: subroutines
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}
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250
main.c
250
main.c
@ -285,7 +285,6 @@ Light ind_lights[] = {
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{ lampsurf, { 1186, 146, 12, 12 }, 0 },
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{ lampsurf, { 1200, 146, 12, 12 }, 0 },
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{ lampsurf, { 1214, 146, 12, 12 }, 0 },
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/* flags */
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/* FE */
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{ lampsurf, { 539, 161, 14, 22 }, 0 },
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{ lampsurf, { 451, 42, 14, 22 }, 0 },
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@ -316,9 +315,79 @@ Light ind_lights[] = {
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{ lampsurf, { 55, 127, 14, 22 }, 0 },
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{ lampsurf, { 55, 144, 14, 22 }, 0 },
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{ lampsurf, { 55, 161, 14, 22 }, 0 },
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/* */
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/* column 2 */
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{ lampsurf, { 99, 42, 14, 22 }, 0 },
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{ lampsurf, { 99, 59, 14, 22 }, 0 },
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{ lampsurf, { 99, 76, 14, 22 }, 0 },
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{ lampsurf, { 99, 93, 14, 22 }, 0 },
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{ lampsurf, { 99, 110, 14, 22 }, 0 },
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{ lampsurf, { 99, 127, 14, 22 }, 0 },
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{ lampsurf, { 99, 144, 14, 22 }, 0 },
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{ lampsurf, { 99, 161, 14, 22 }, 0 },
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/* column 3 */
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{ lampsurf, { 143, 42, 14, 22 }, 0 },
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{ lampsurf, { 143, 59, 14, 22 }, 0 },
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{ lampsurf, { 143, 76, 14, 22 }, 0 },
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{ lampsurf, { 143, 93, 14, 22 }, 0 },
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{ lampsurf, { 143, 110, 14, 22 }, 0 },
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{ lampsurf, { 143, 127, 14, 22 }, 0 },
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{ lampsurf, { 143, 144, 14, 22 }, 0 },
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{ lampsurf, { 143, 162, 14, 22 }, 0 },
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/* column 4 */
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{ lampsurf, { 187, 42, 14, 22 }, 0 },
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{ lampsurf, { 187, 59, 14, 22 }, 0 },
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{ lampsurf, { 187, 76, 14, 22 }, 0 },
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{ lampsurf, { 187, 93, 14, 22 }, 0 },
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{ lampsurf, { 187, 110, 14, 22 }, 0 },
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{ lampsurf, { 187, 127, 14, 22 }, 0 },
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{ lampsurf, { 187, 144, 14, 22 }, 0 },
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{ lampsurf, { 187, 162, 14, 22 }, 0 },
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/* column 5 */
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{ lampsurf, { 231, 42, 14, 22 }, 0 },
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{ lampsurf, { 231, 59, 14, 22 }, 0 },
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{ lampsurf, { 231, 76, 14, 22 }, 0 },
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{ lampsurf, { 231, 93, 14, 22 }, 0 },
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{ lampsurf, { 231, 110, 14, 22 }, 0 },
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{ lampsurf, { 231, 127, 14, 22 }, 0 },
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{ lampsurf, { 231, 144, 14, 22 }, 0 },
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{ lampsurf, { 231, 162, 14, 22 }, 0 },
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/* column 6 */
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{ lampsurf, { 275, 42, 14, 22 }, 0 },
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{ lampsurf, { 275, 59, 14, 22 }, 0 },
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{ lampsurf, { 275, 76, 14, 22 }, 0 },
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{ lampsurf, { 275, 93, 14, 22 }, 0 },
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{ lampsurf, { 275, 110, 14, 22 }, 0 },
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{ lampsurf, { 275, 127, 14, 22 }, 0 },
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{ lampsurf, { 275, 144, 14, 22 }, 0 },
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{ lampsurf, { 275, 162, 14, 22 }, 0 },
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/* column 7 */
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{ lampsurf, { 319, 42, 14, 22 }, 0 },
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{ lampsurf, { 319, 59, 14, 22 }, 0 },
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{ lampsurf, { 319, 76, 14, 22 }, 0 },
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{ lampsurf, { 319, 93, 14, 22 }, 0 },
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{ lampsurf, { 319, 110, 14, 22 }, 0 },
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{ lampsurf, { 319, 127, 14, 22 }, 0 },
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{ lampsurf, { 319, 144, 14, 22 }, 0 },
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{ lampsurf, { 319, 161, 14, 22 }, 0 },
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/* column 8 */
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{ lampsurf, { 363, 42, 14, 22 }, 0 },
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{ lampsurf, { 363, 59, 14, 22 }, 0 },
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{ lampsurf, { 363, 76, 14, 22 }, 0 },
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{ lampsurf, { 363, 93, 14, 22 }, 0 },
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{ lampsurf, { 363, 110, 14, 22 }, 0 },
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{ lampsurf, { 363, 127, 14, 22 }, 0 },
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{ lampsurf, { 363, 144, 14, 22 }, 0 },
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{ lampsurf, { 363, 161, 14, 22 }, 0 },
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/* column 9 */
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{ lampsurf, { 407, 42, 14, 22 }, 0 },
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{ lampsurf, { 407, 59, 14, 22 }, 0 },
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{ lampsurf, { 407, 76, 14, 22 }, 0 },
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{ lampsurf, { 407, 93, 14, 22 }, 0 },
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{ lampsurf, { 407, 110, 14, 22 }, 0 },
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{ lampsurf, { 407, 127, 14, 22 }, 0 },
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{ lampsurf, { 407, 144, 14, 22 }, 0 },
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{ lampsurf, { 407, 161, 14, 22 }, 0 },
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/* FE and SC see above */
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/* column 12 */
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{ lampsurf, { 539, 42, 14, 22 }, 0 },
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{ lampsurf, { 539, 59, 14, 22 }, 0 },
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@ -326,6 +395,8 @@ Light ind_lights[] = {
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{ lampsurf, { 539, 93, 14, 22 }, 0 },
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{ lampsurf, { 539, 110, 14, 22 }, 0 },
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{ lampsurf, { 539, 127, 14, 22 }, 0 },
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/* SC0 *
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* FE0 */
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/* column 13 */
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{ lampsurf, { 583, 42, 14, 22 }, 0 },
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{ lampsurf, { 583, 59, 14, 22 }, 0 },
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@ -344,34 +415,6 @@ Light ind_lights[] = {
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{ lampsurf, { 627, 127, 14, 22 }, 0 },
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{ lampsurf, { 627, 144, 14, 22 }, 0 },
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{ lampsurf, { 627, 161, 14, 22 }, 0 },
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/* column 9 */
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{ lampsurf, { 407, 42, 14, 22 }, 0 },
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{ lampsurf, { 407, 59, 14, 22 }, 0 },
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{ lampsurf, { 407, 76, 14, 22 }, 0 },
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{ lampsurf, { 407, 93, 14, 22 }, 0 },
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{ lampsurf, { 407, 110, 14, 22 }, 0 },
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{ lampsurf, { 407, 127, 14, 22 }, 0 },
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{ lampsurf, { 407, 144, 14, 22 }, 0 },
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{ lampsurf, { 407, 161, 14, 22 }, 0 },
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/* sbr flip-flops */
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{ lampsurf, { 99, 42, 14, 22 }, 0 },
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{ lampsurf, { 99, 59, 14, 22 }, 0 },
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{ lampsurf, { 99, 76, 14, 22 }, 0 },
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{ lampsurf, { 99, 93, 14, 22 }, 0 },
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{ lampsurf, { 99, 110, 14, 22 }, 0 },
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{ lampsurf, { 99, 127, 14, 22 }, 0 },
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{ lampsurf, { 99, 144, 14, 22 }, 0 },
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{ lampsurf, { 99, 161, 14, 22 }, 0 },
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{ lampsurf, { 143, 42, 14, 22 }, 0 },
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{ lampsurf, { 143, 59, 14, 22 }, 0 },
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{ lampsurf, { 143, 76, 14, 22 }, 0 },
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{ lampsurf, { 143, 93, 14, 22 }, 0 },
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{ lampsurf, { 143, 110, 14, 22 }, 0 }, // BLT
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{ lampsurf, { 143, 127, 14, 22 }, 0 },
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{ lampsurf, { 143, 144, 14, 22 }, 0 },
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{ lampsurf, { 143, 162, 14, 22 }, 0 }, // IOT
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{ lampsurf, { 319, 144, 14, 22 }, 0 }, // shf1
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{ lampsurf, { 319, 161, 14, 22 }, 0 }, // sc=777
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};
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Light extra_lights[] = {
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@ -830,56 +873,103 @@ error:
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ff_lght[5].state = apr.mc_rd;
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ff_lght[6].state = apr.mc_wr;
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ff_lght[7].state = apr.mc_rq;
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ff_lght[8].state = apr.mc_split_cyc_sync;
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ff_lght[9].state = apr.mc_stop_sync;
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ff_lght[10].state = !apr.ex_user;
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ff_lght[11].state = apr.cpa_illeg_op;
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ff_lght[12].state = apr.ex_ill_op;
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ff_lght[13].state = apr.ex_uuo_sync;
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ff_lght[14].state = apr.ex_pi_sync;
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ff_lght[15].state = apr.mq36;
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ff_lght[16].state = apr.key_rim_sbr;
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ff_lght[17].state = apr.ar_cry0_xor_cry1;
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ff_lght[18].state = apr.ar_cry0;
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ff_lght[19].state = apr.ar_cry1;
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ff_lght[20].state = apr.ar_ov_flag;
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ff_lght[21].state = apr.ar_cry0_flag;
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ff_lght[22].state = apr.ar_cry1_flag;
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ff_lght[23].state = apr.ar_pc_chg_flag;
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ff_lght[24].state = apr.cpa_non_exist_mem;
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ff_lght[25].state = apr.cpa_clock_enable;
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ff_lght[26].state = apr.cpa_clock_flag;
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ff_lght[27].state = apr.cpa_pc_chg_enable;
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ff_lght[28].state = apr.cpa_arov_enable;
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ff_lght[29].state = !!(apr.cpa_pia&4);
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ff_lght[30].state = !!(apr.cpa_pia&2);
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ff_lght[31].state = !!(apr.cpa_pia&1);
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ff_lght[32].state = apr.pi_ov;
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ff_lght[33].state = apr.pi_cyc;
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ff_lght[34].state = !!apr.pi_req;
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ff_lght[35].state = apr.iot_go;
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ff_lght[36].state = apr.a_long;
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ff_lght[37].state = apr.ma == apr.mas;
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ff_lght[38].state = apr.uuo_f1;
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ff_lght[39].state = apr.cpa_pdl_ov;
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ff_lght[40].state = apr.if1a;
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ff_lght[41].state = apr.af0;
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ff_lght[42].state = apr.af3;
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ff_lght[43].state = apr.af3a;
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ff_lght[44].state = apr.et4_ar_pse;
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ff_lght[45].state = apr.f1a;
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ff_lght[46].state = apr.f4a;
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ff_lght[47].state = apr.f6a;
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ff_lght[48].state = apr.sf3;
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ff_lght[49].state = apr.sf5a;
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ff_lght[50].state = apr.sf7;
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ff_lght[51].state = apr.ar_com_cont;
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ff_lght[52].state = apr.blt_f0a;
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ff_lght[53].state = apr.blt_f3a;
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ff_lght[54].state = apr.blt_f5a;
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ff_lght[55].state = apr.iot_f0a;
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ff_lght[56].state = apr.shf1;
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ff_lght[57].state = apr.sc == 0777;
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ff_lght[8].state = apr.if1a;
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ff_lght[9].state = apr.af0;
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ff_lght[10].state = apr.af3;
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ff_lght[11].state = apr.af3a;
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ff_lght[12].state = apr.et4_ar_pse;
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ff_lght[13].state = apr.f1a;
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ff_lght[14].state = apr.f4a;
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ff_lght[15].state = apr.f6a;
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ff_lght[16].state = apr.sf3;
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ff_lght[17].state = apr.sf5a;
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ff_lght[18].state = apr.sf7;
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ff_lght[19].state = apr.ar_com_cont;
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ff_lght[20].state = apr.blt_f0a;
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ff_lght[21].state = apr.blt_f3a;
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ff_lght[22].state = apr.blt_f5a;
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ff_lght[23].state = apr.iot_f0a;
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ff_lght[24].state = 0;
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ff_lght[25].state = 0;
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ff_lght[26].state = 0;
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ff_lght[27].state = 0;
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ff_lght[28].state = 0;
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ff_lght[29].state = 0;
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ff_lght[30].state = 0;
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ff_lght[31].state = 0;
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ff_lght[32].state = 0;
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ff_lght[33].state = 0;
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ff_lght[34].state = 0;
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ff_lght[35].state = 0;
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ff_lght[36].state = 0;
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ff_lght[37].state = 0;
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ff_lght[38].state = 0;
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ff_lght[39].state = 0;
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ff_lght[40].state = 0;
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ff_lght[41].state = 0;
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ff_lght[42].state = 0;
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ff_lght[43].state = 0;
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ff_lght[44].state = 0;
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ff_lght[45].state = 0;
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ff_lght[46].state = 0;
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ff_lght[47].state = 0;
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ff_lght[48].state = 0;
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ff_lght[49].state = 0;
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ff_lght[50].state = 0;
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ff_lght[51].state = 0;
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ff_lght[52].state = apr.mc_split_cyc_sync;
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ff_lght[53].state = apr.mc_stop_sync;
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ff_lght[54].state = apr.shf1;
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ff_lght[55].state = apr.sc == 0777;
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ff_lght[56].state = apr.chf1;
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ff_lght[57].state = apr.chf2;
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ff_lght[58].state = apr.chf3;
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ff_lght[59].state = apr.chf4;
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ff_lght[60].state = apr.chf5;
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ff_lght[61].state = apr.chf6;
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ff_lght[62].state = apr.lcf1;
|
||||
ff_lght[63].state = apr.dcf1;
|
||||
|
||||
ff_lght[64].state = apr.pi_ov;
|
||||
ff_lght[65].state = apr.pi_cyc;
|
||||
ff_lght[66].state = !!apr.pi_req;
|
||||
ff_lght[67].state = apr.iot_go;
|
||||
ff_lght[68].state = apr.a_long;
|
||||
ff_lght[69].state = apr.ma == apr.mas;
|
||||
ff_lght[70].state = apr.uuo_f1;
|
||||
ff_lght[71].state = apr.cpa_pdl_ov;
|
||||
|
||||
ff_lght[72].state = !apr.ex_user;
|
||||
ff_lght[73].state = apr.cpa_illeg_op;
|
||||
ff_lght[74].state = apr.ex_ill_op;
|
||||
ff_lght[75].state = apr.ex_uuo_sync;
|
||||
ff_lght[76].state = apr.ex_pi_sync;
|
||||
ff_lght[77].state = apr.mq36;
|
||||
|
||||
ff_lght[78].state = apr.key_rim_sbr;
|
||||
ff_lght[79].state = apr.ar_cry0_xor_cry1;
|
||||
ff_lght[80].state = apr.ar_cry0;
|
||||
ff_lght[81].state = apr.ar_cry1;
|
||||
ff_lght[82].state = apr.ar_ov_flag;
|
||||
ff_lght[83].state = apr.ar_cry0_flag;
|
||||
ff_lght[84].state = apr.ar_cry1_flag;
|
||||
ff_lght[85].state = apr.ar_pc_chg_flag;
|
||||
|
||||
ff_lght[86].state = apr.cpa_non_exist_mem;
|
||||
ff_lght[87].state = apr.cpa_clock_enable;
|
||||
ff_lght[88].state = apr.cpa_clock_flag;
|
||||
ff_lght[89].state = apr.cpa_pc_chg_enable;
|
||||
ff_lght[90].state = apr.cpa_arov_enable;
|
||||
ff_lght[91].state = !!(apr.cpa_pia&4);
|
||||
ff_lght[92].state = !!(apr.cpa_pia&2);
|
||||
ff_lght[93].state = !!(apr.cpa_pia&1);
|
||||
|
||||
setlights(membus0, membus_lght, 36);
|
||||
setlights(apr.pr, pr_lght, 8);
|
||||
|
||||
2
mem
2
mem
@ -1,4 +1,4 @@
|
||||
1000: 201040000002
|
||||
1001: 505040440700
|
||||
1002: 134140000001
|
||||
1002: 136200000001
|
||||
1003: 254200000000
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user