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rewrote the verilog code

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aap
2016-11-13 02:06:34 +01:00
parent fb47930b1b
commit 14a82a7e61
10 changed files with 2520 additions and 1566 deletions
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4
verilog/Makefile
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@@ -1,5 +1,5 @@
a.out: test.v apr.v coremem.v fastmem.v modules.v
iverilog test.v apr.v coremem.v fastmem.v modules.v
a.out: test.v pdp6.v apr.v core161c.v fast162.v modules.v
iverilog test.v pdp6.v apr.v core161c.v fast162.v modules.v
run: a.out
vvp a.out

1700
verilog/apr.v
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File diff suppressed because it is too large Load Diff

315
verilog/core161c.v Normal file
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module core161c(
input wire clk,
input wire reset,
input wire power,
input wire sw_single_step,
input wire sw_restart,
input wire membus_wr_rs_p0,
input wire membus_rq_cyc_p0,
input wire membus_rd_rq_p0,
input wire membus_wr_rq_p0,
input wire [21:35] membus_ma_p0,
input wire [18:21] membus_sel_p0,
input wire membus_fmc_select_p0,
input wire [0:35] membus_mb_in_p0,
output wire membus_addr_ack_p0,
output wire membus_rd_rs_p0,
output wire [0:35] membus_mb_out_p0,
input wire membus_wr_rs_p1,
input wire membus_rq_cyc_p1,
input wire membus_rd_rq_p1,
input wire membus_wr_rq_p1,
input wire [21:35] membus_ma_p1,
input wire [18:21] membus_sel_p1,
input wire membus_fmc_select_p1,
input wire [0:35] membus_mb_in_p1,
output wire membus_addr_ack_p1,
output wire membus_rd_rs_p1,
output wire [0:35] membus_mb_out_p1,
input wire membus_wr_rs_p2,
input wire membus_rq_cyc_p2,
input wire membus_rd_rq_p2,
input wire membus_wr_rq_p2,
input wire [21:35] membus_ma_p2,
input wire [18:21] membus_sel_p2,
input wire membus_fmc_select_p2,
input wire [0:35] membus_mb_in_p2,
output wire membus_addr_ack_p2,
output wire membus_rd_rs_p2,
output wire [0:35] membus_mb_out_p2,
input wire membus_wr_rs_p3,
input wire membus_rq_cyc_p3,
input wire membus_rd_rq_p3,
input wire membus_wr_rq_p3,
input wire [21:35] membus_ma_p3,
input wire [18:21] membus_sel_p3,
input wire membus_fmc_select_p3,
input wire [0:35] membus_mb_in_p3,
output wire membus_addr_ack_p3,
output wire membus_rd_rs_p3,
output wire [0:35] membus_mb_out_p3
);
/* Jumpers */
reg [0:3] memsel_p0;
reg [0:3] memsel_p1;
reg [0:3] memsel_p2;
reg [0:3] memsel_p3;
reg [22:35] cma;
reg cma_rd_rq;
reg cma_wr_rq;
reg [0:35] cmb;
reg cmc_p0_act, cmc_p1_act, cmc_p2_act, cmc_p3_act;
reg cmc_last_proc;
reg cmc_rd;
reg cmc_inhibit;
reg cmc_wr;
reg cmc_await_rq;
reg cmc_proc_rs;
reg cmc_pse_sync;
reg cmc_stop;
reg [0:36] core[0:040000];
wire cyc_rq_p0 = memsel_p0 == membus_sel_p0 &
~membus_fmc_select_p0 & membus_rq_cyc_p0;
wire cyc_rq_p1 = memsel_p1 == membus_sel_p1 &
~membus_fmc_select_p1 & membus_rq_cyc_p1;
wire cyc_rq_p2 = memsel_p2 == membus_sel_p2 &
~membus_fmc_select_p2 & membus_rq_cyc_p2;
wire cyc_rq_p3 = memsel_p3 == membus_sel_p3 &
~membus_fmc_select_p3 & membus_rq_cyc_p3;
wire cmpc_p0_rq = cyc_rq_p0 & cmc_await_rq;
wire cmpc_p1_rq = cyc_rq_p1 & cmc_await_rq;
wire cmpc_p2_rq = cyc_rq_p2 & cmc_await_rq;
wire cmpc_p3_rq = cyc_rq_p3 & cmc_await_rq;
wire wr_rs = cmc_p0_act ? membus_wr_rs_p0 :
cmc_p1_act ? membus_wr_rs_p1 :
cmc_p2_act ? membus_wr_rs_p2 :
cmc_p3_act ? membus_wr_rs_p3 : 0;
wire rq_cyc = cmc_p0_act ? membus_rq_cyc_p0 :
cmc_p1_act ? membus_rq_cyc_p1 :
cmc_p2_act ? membus_rq_cyc_p2 :
cmc_p3_act ? membus_rq_cyc_p3 : 0;
wire rd_rq = cmc_p0_act ? membus_rd_rq_p0 :
cmc_p1_act ? membus_rd_rq_p1 :
cmc_p2_act ? membus_rd_rq_p2 :
cmc_p3_act ? membus_rd_rq_p3 : 0;
wire wr_rq = cmc_p0_act ? membus_wr_rq_p0 :
cmc_p1_act ? membus_wr_rq_p1 :
cmc_p2_act ? membus_wr_rq_p2 :
cmc_p3_act ? membus_wr_rq_p3 : 0;
wire [21:35] ma = cmc_p0_act ? membus_ma_p0 :
cmc_p1_act ? membus_ma_p1 :
cmc_p2_act ? membus_ma_p2 :
cmc_p3_act ? membus_ma_p3 : 0;
wire [0:35] mb_in = cmc_p0_act ? membus_mb_in_p0 :
cmc_p1_act ? membus_mb_in_p1 :
cmc_p2_act ? membus_mb_in_p2 :
cmc_p3_act ? membus_mb_in_p3 : 0;
assign membus_addr_ack_p0 = cmc_addr_ack & cmc_p0_act;
assign membus_rd_rs_p0 = cmc_rd_rs & cmc_p0_act;
assign membus_mb_out_p0 = cmc_p0_act ? mb_out : 0;
assign membus_addr_ack_p1 = cmc_addr_ack & cmc_p1_act;
assign membus_rd_rs_p1 = cmc_rd_rs & cmc_p1_act;
assign membus_mb_out_p1 = cmc_p1_act ? mb_out : 0;
assign membus_addr_ack_p2 = cmc_addr_ack & cmc_p2_act;
assign membus_rd_rs_p2 = cmc_rd_rs & cmc_p2_act;
assign membus_mb_out_p2 = cmc_p2_act ? mb_out : 0;
assign membus_addr_ack_p3 = cmc_addr_ack & cmc_p3_act;
assign membus_rd_rs_p3 = cmc_rd_rs & cmc_p3_act;
assign membus_mb_out_p3 = cmc_p3_act ? mb_out : 0;
wire cmc_addr_ack;
wire cmc_rd_rs;
wire [0:35] mb_out = mb_pulse_out ? core[cma] : 0;
wire cmpc_rs_strb;
wire cmc_pwr_clr;
wire cmc_pwr_start;
wire cmc_key_restart;
wire cmc_state_clr;
wire cmc_cmb_clr;
wire cmc_strb_sa;
wire cmc_proc_rs_P;
wire mb_pulse_out;
wire mb_pulse_in;
wire cmc_wr_rs;
wire cmc_t0;
wire cmc_t1;
wire cmc_t2;
wire cmc_t4;
wire cmc_t5;
wire cmc_t6;
wire cmc_t7;
wire cmc_t8;
wire cmc_t9;
wire cmc_t9a;
wire cmc_t10;
wire cmc_t11;
wire cmc_t12;
// power-on timing is totally wrong
pg cmc_pg0(.clk(clk), .reset(reset), .in(power), .p(cmc_pwr_clr));
pg cmc_pg1(.clk(clk), .reset(reset),
.in(sw_restart & cmc_stop), .p(cmc_key_restart));
pg cmc_pg2(.clk(clk), .reset(reset),
.in(cmpc_p0_rq | cmpc_p1_rq | cmpc_p2_rq | cmpc_p3_rq),
.p(cmc_t0));
pg cmc_pg3(.clk(clk), .reset(reset), .in(| mb_in), .p(mb_pulse_in));
pg cmc_pg4(.clk(clk), .reset(reset), .in(wr_rs), .p(cmpc_rs_strb));
pg cmc_pg5(.clk(clk), .reset(reset), .in(cmc_proc_rs), .p(cmc_proc_rs_P));
pg cmc_pg6(.clk(clk), .reset(reset), .in(cmc_pse_sync & cmc_proc_rs), .p(cmc_wr_rs));
pa cmc_pa0(.clk(clk), .reset(reset), .in(cmc_pwr_clr | cmc_t9a_D), .p(cmc_t12));
pa cmc_pa1(.clk(clk), .reset(reset), .in(cmc_pwr_clr_D), .p(cmc_pwr_start));
pa cmc_pa2(.clk(clk), .reset(reset),
.in(cmc_t9a & ~cmc_stop | cmc_pwr_start | cmc_key_restart),
.p(cmc_t10));
pa cmc_pa3(.clk(clk), .reset(reset), .in(cmc_t10_D), .p(cmc_t11));
pa cmc_pa4(.clk(clk), .reset(reset),
.in(cmc_t10 | ~cma_wr_rq & cmc_strb_sa_D1 | cmc_proc_rs_P),
.p(cmc_state_clr));
pa cmc_pa5(.clk(clk), .reset(reset),
.in(cmc_t0 | cmc_strb_sa_D2 & cma_wr_rq),
.p(cmc_cmb_clr));
pa cmc_pa6(.clk(clk), .reset(reset), .in(cmc_t0_D), .p(cmc_t1));
pa cmc_pa7(.clk(clk), .reset(reset), .in(cmc_t1_D), .p(cmc_t2));
pa cmc_pa8(.clk(clk), .reset(reset), .in(cmc_t2_D0), .p(cmc_t4));
pa cmc_pa9(.clk(clk), .reset(reset), .in(cmc_t4_D), .p(cmc_t5));
pa cmc_pa10(.clk(clk), .reset(reset),
.in(cmc_t5 & ~cma_wr_rq | cmc_wr_rs),
.p(cmc_t6));
pa cmc_pa11(.clk(clk), .reset(reset), .in(cmc_t6_D), .p(cmc_t7));
pa cmc_pa12(.clk(clk), .reset(reset), .in(cmc_t7_D), .p(cmc_t8));
pa cmc_pa13(.clk(clk), .reset(reset), .in(cmc_t8_D), .p(cmc_t9));
pa cmc_pa14(.clk(clk), .reset(reset), .in(cmc_t9_D), .p(cmc_t9a));
pa cmc_pa15(.clk(clk), .reset(reset),
.in(cmc_t2_D1 & cma_rd_rq),
.p(cmc_strb_sa));
// not on schematics
bd cmc_bd0(.clk(clk), .reset(reset), .in(cmc_t1), .p(cmc_addr_ack));
bd cmc_bd1(.clk(clk), .reset(reset), .in(cmc_strb_sa_D0), .p(cmc_rd_rs));
bd2 cmc_bd2(.clk(clk), .reset(reset), .in(cmc_strb_sa), .p(mb_pulse_out));
wire cmc_pwr_clr_D;
wire cmc_t0_D, cmc_t1_D, cmc_t2_D0, cmc_t2_D1, cmc_t4_D;
wire cmc_t6_D, cmc_t7_D, cmc_t8_D, cmc_t9_D, cmc_t9a_D, cmc_t10_D;
wire cmc_strb_sa_D0, cmc_strb_sa_D1, cmc_strb_sa_D2;
dly100ns cmc_dly0(.clk(clk), .reset(reset), .in(cmc_pwr_clr), .p(cmc_pwr_clr_D));
dly100ns cmc_dly1(.clk(clk), .reset(reset), .in(cmc_t10), .p(cmc_t10_D));
dly200ns cmc_dly2(.clk(clk), .reset(reset), .in(cmc_t0), .p(cmc_t0_D));
dly1us cmc_dly3(.clk(clk), .reset(reset), .in(cmc_t1), .p(cmc_t1_D));
dly1us cmc_dly4(.clk(clk), .reset(reset), .in(cmc_t2), .p(cmc_t2_D0));
dly200ns cmc_dly5(.clk(clk), .reset(reset), .in(cmc_t4), .p(cmc_t4_D));
dly200ns cmc_dly6(.clk(clk), .reset(reset), .in(cmc_t6), .p(cmc_t6_D));
dly200ns cmc_dly7(.clk(clk), .reset(reset), .in(cmc_t7), .p(cmc_t7_D));
dly1us cmc_dly8(.clk(clk), .reset(reset), .in(cmc_t8), .p(cmc_t8_D));
dly400ns cmc_dly9(.clk(clk), .reset(reset), .in(cmc_t9), .p(cmc_t9_D));
dly200ns cmc_dly10(.clk(clk), .reset(reset), .in(cmc_t9a), .p(cmc_t9a_D));
dly800ns cmc_dly11(.clk(clk), .reset(reset), .in(cmc_t2), .p(cmc_t2_D1));
dly100ns cmc_dly12(.clk(clk), .reset(reset),
.in(cmc_strb_sa), .p(cmc_strb_sa_D0));
dly200ns cmc_dly13(.clk(clk), .reset(reset),
.in(cmc_strb_sa), .p(cmc_strb_sa_D1));
dly250ns cmc_dly14(.clk(clk), .reset(reset),
.in(cmc_strb_sa), .p(cmc_strb_sa_D2));
always @(posedge reset) begin
cmc_await_rq <= 0;
cmc_last_proc <= 0;
cmc_proc_rs <= 0;
end
wire [0:35] corescope = core[cma];
always @(posedge clk) begin
if(cmc_state_clr) begin
cmc_p0_act <= 0;
cmc_p1_act <= 0;
cmc_p2_act <= 0;
cmc_p3_act <= 0;
end
if(cmc_cmb_clr)
cmb <= 0;
if(cmc_strb_sa)
cmb <= cmb | core[cma];
if(mb_pulse_in)
cmb <= cmb | mb_in;
if(cmpc_rs_strb)
cmc_proc_rs <= 1;
if(cmc_t0) begin
cmc_await_rq <= 0;
cmc_proc_rs <= 0;
cmc_pse_sync <= 0;
cmc_stop <= 0;
cma <= 0;
cma_rd_rq <= 0;
cma_wr_rq <= 0;
// this happens between t0 and t1 */
if(cmpc_p0_rq)
cmc_p0_act <= 1;
else if(cmpc_p1_rq)
cmc_p1_act <= 1;
else if(cmpc_p2_rq) begin
if(~cmpc_p3_rq | cmc_last_proc)
cmc_p2_act <= 1;
end else if(cmpc_p3_rq) begin
if(~cmpc_p2_rq | ~cmc_last_proc)
cmc_p3_act <= 1;
end
end
if(cmc_t1) begin // this seems to be missing from the schematics
cma <= cma | ma;
if(rd_rq)
cma_rd_rq <= 1;
if(wr_rq)
cma_wr_rq <= 1;
end
if(cmc_t2) begin
cmc_rd <= 1;
if(cmc_p2_act)
cmc_last_proc <= 0;
if(cmc_p3_act)
cmc_last_proc <= 1;
end
if(cmc_t4)
/* As a hack zero core here */
core[cma] <= 0;
if(cmc_t5) begin
cmc_rd <= 0;
cmc_pse_sync <= 1;
end
if(cmc_t7) begin
cmc_inhibit <= 1;
if(sw_single_step)
cmc_stop <= 1;
end
if(cmc_t8)
cmc_wr <= 1;
if(cmc_t9 & cmc_wr)
/* again a hack. core is written some time after t8.
* (cmc_wr is always set here) */
core[cma] <= core[cma] | cmb;
if(cmc_t11)
cmc_await_rq <= 1;
if(cmc_t12) begin
cmc_rd <= 0;
cmc_inhibit <= 0;
cmc_wr <= 0;
end
end
endmodule

255
verilog/coremem.v
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@@ -1,255 +0,0 @@
module coremem16k(
input clk,
input mc_wr_rs_p0,
input mc_rq_cyc_p0,
input mc_rd_rq_p0,
input mc_wr_rq_p0,
input [21:35] ma_p0,
input [18:21] sel_p0,
input fmc_select_p0,
input [0:35] mb_in_p0,
output cmc_addr_ack_p0,
output cmc_rd_rs_p0,
output [0:35] mb_out_p0,
input mc_wr_rs_p1,
input mc_rq_cyc_p1,
input mc_rd_rq_p1,
input mc_wr_rq_p1,
input [21:35] ma_p1,
input [18:21] sel_p1,
input fmc_select_p1,
input [0:35] mb_in_p1,
output cmc_addr_ack_p1,
output cmc_rd_rs_p1,
output [0:35] mb_out_p1,
input mc_wr_rs_p2,
input mc_rq_cyc_p2,
input mc_rd_rq_p2,
input mc_wr_rq_p2,
input [21:35] ma_p2,
input [18:21] sel_p2,
input fmc_select_p2,
input [0:35] mb_in_p2,
output cmc_addr_ack_p2,
output cmc_rd_rs_p2,
output [0:35] mb_out_p2,
input mc_wr_rs_p3,
input mc_rq_cyc_p3,
input mc_rd_rq_p3,
input mc_wr_rq_p3,
input [21:35] ma_p3,
input [18:21] sel_p3,
input fmc_select_p3,
input [0:35] mb_in_p3,
output cmc_addr_ack_p3,
output cmc_rd_rs_p3,
output [0:35] mb_out_p3
);
wire [21:35] ma;
wire [0:35] mb_out;
wire [0:35] mb_in;
wire cmc_power_start;
reg power;
reg single_step_sw;
reg restart_sw;
reg [0:3] memsel_p0;
reg [0:3] memsel_p1;
reg [0:3] memsel_p2;
reg [0:3] memsel_p3;
reg cmc_p0_act, cmc_p1_act, cmc_p2_act, cmc_p3_act;
reg cmc_last_proc;
reg cmc_aw_rq, cmc_proc_rs, cmc_pse_sync, cmc_stop;
reg cmc_rd, cmc_wr, cmc_inhibit;
reg [0:35] cmb;
reg [22:35] cma;
reg cma_rd_rq, cma_wr_rq;
reg [0:36] core[0:040000];
assign cyc_rq_p0 = memsel_p0 == sel_p0 & ~fmc_select_p0 & mc_rq_cyc_p0;
assign cyc_rq_p1 = memsel_p1 == sel_p1 & ~fmc_select_p1 & mc_rq_cyc_p1;
assign cyc_rq_p2 = memsel_p2 == sel_p2 & ~fmc_select_p2 & mc_rq_cyc_p2;
assign cyc_rq_p3 = memsel_p3 == sel_p3 & ~fmc_select_p3 & mc_rq_cyc_p3;
assign cmpc_p0_rq = cyc_rq_p0 & cmc_aw_rq;
assign cmpc_p1_rq = cyc_rq_p1 & cmc_aw_rq;
assign cmpc_p2_rq = cyc_rq_p2 & cmc_aw_rq;
assign cmpc_p3_rq = cyc_rq_p3 & cmc_aw_rq;
// simulate power on
initial begin
power = 0;
cmc_aw_rq = 0;
cmc_rd = 0;
cmc_wr = 0;
single_step_sw = 0;
restart_sw = 0;
cmc_proc_rs = 0;
cmc_pse_sync = 0;
cmc_last_proc = 0;
#500;
power = 1;
end
// there has to be a better way....
// from proc to mem
assign mc_wr_rs = cmc_p0_act ? mc_wr_rs_p0 :
cmc_p1_act ? mc_wr_rs_p1 :
cmc_p2_act ? mc_wr_rs_p2 :
cmc_p3_act ? mc_wr_rs_p3 : 0;
assign mc_rq_cyc = cmc_p0_act ? mc_rq_cyc_p0 :
cmc_p1_act ? mc_rq_cyc_p1 :
cmc_p2_act ? mc_rq_cyc_p2 :
cmc_p3_act ? mc_rq_cyc_p3 : 0;
assign mc_rd_rq = cmc_p0_act ? mc_rd_rq_p0 :
cmc_p1_act ? mc_rd_rq_p1 :
cmc_p2_act ? mc_rd_rq_p2 :
cmc_p3_act ? mc_rd_rq_p3 : 0;
assign mc_wr_rq = cmc_p0_act ? mc_wr_rq_p0 :
cmc_p1_act ? mc_wr_rq_p1 :
cmc_p2_act ? mc_wr_rq_p2 :
cmc_p3_act ? mc_wr_rq_p3 : 0;
assign ma = cmc_p0_act ? ma_p0 :
cmc_p1_act ? ma_p1 :
cmc_p2_act ? ma_p2 :
cmc_p3_act ? ma_p3 : 0;
assign mb_in = cmc_p0_act ? mb_in_p0 :
cmc_p1_act ? mb_in_p1 :
cmc_p2_act ? mb_in_p2 :
cmc_p3_act ? mb_in_p3 : 0;
// from mem to proc
assign cmc_addr_ack_p0 = cmc_addr_ack & cmc_p0_act;
assign cmc_rd_rs_p0 = cmc_rd_rs & cmc_p0_act;
assign mb_out_p0 = cmc_p0_act ? mb_out : 0;
assign cmc_addr_ack_p1 = cmc_addr_ack & cmc_p1_act;
assign cmc_rd_rs_p1 = cmc_rd_rs & cmc_p1_act;
assign mb_out_p1 = cmc_p1_act ? mb_out : 0;
assign cmc_addr_ack_p2 = cmc_addr_ack & cmc_p2_act;
assign cmc_rd_rs_p2 = cmc_rd_rs & cmc_p2_act;
assign mb_out_p2 = cmc_p2_act ? mb_out : 0;
assign cmc_addr_ack_p3 = cmc_addr_ack & cmc_p3_act;
assign cmc_rd_rs_p3 = cmc_rd_rs & cmc_p3_act;
assign mb_out_p3 = cmc_p3_act ? mb_out : 0;
syncpulse synccmc0(.clk(clk), .in(cmc_aw_rq & mc_rq_cyc), .out(cmc_t0));
syncpulse synccmc2(.clk(clk), .in(mc_wr_rs), .out(mc_wr_rs_S));
dly200ns cmcdly1(.clk(clk), .in(cmc_t0), .out(cmc_t1));
assign cmc_addr_ack = cmc_t1;
dly1000ns cmcdly2(.clk(clk), .in(cmc_t1), .out(cmc_t2));
dly1000ns cmcdly3(.clk(clk), .in(cmc_t2), .out(cmc_t4));
dly200ns cmcdly4(.clk(clk), .in(cmc_t4), .out(cmc_t5));
assign cmc_t6 = cmc_t5 & ~cma_wr_rq | cmc_tmp4;
dly200ns cmcdly9(.clk(clk), .in(cmc_t6), .out(cmc_t7));
dly200ns cmcdly10(.clk(clk), .in(cmc_t7), .out(cmc_t8));
dly1000ns cmcdly11(.clk(clk), .in(cmc_t8), .out(cmc_t9));
dly400ns cmcdly12(.clk(clk), .in(cmc_t9), .out(cmc_t9a));
assign cmc_t10 = cmc_t9a & ~cmc_stop | cmc_pwr_start;
dly100ns cmcdly13(.clk(clk), .in(cmc_t10), .out(cmc_t11));
dly200ns cmcdly14(.clk(clk), .in(cmc_t9a), .out(cmc_t12));
dly800ns cmcdly5(.clk(clk), .in(cmc_t2), .out(cmc_tmp1));
assign cmc_strb_sa = cmc_tmp1 & cma_rd_rq;
dly100ns cmcdly6(.clk(clk), .in(cmc_strb_sa), .out(cmc_rd_rs));
dly250ns cmcdly7(.clk(clk), .in(cmc_strb_sa), .out(cmc_tmp2));
dly200ns cmcdly8(.clk(clk), .in(cmc_strb_sa), .out(cmc_tmp3));
assign cmc_cmb_clr = cmc_t0 | cmc_tmp2 & cma_wr_rq;
assign cmc_state_clr = cmc_tmp3 & ~cma_wr_rq | cmc_t10 | cmc_proc_rs1;
syncpulse synccmc1(.clk(clk), .in(| mb_in), .out(mb_pulse));
syncpulse synccmc3(.clk(clk), .in(cmc_proc_rs & cmc_pse_sync), .out(cmc_tmp4));
syncpulse synccmc4(.clk(clk), .in(cmc_proc_rs), .out(cmc_proc_rs1));
syncpulse synccmc5(.clk(clk), .in(power), .out(cmc_pwr_start));
// generate a longer pulse so processor has time to read
pa100ns cmcpa0(.clk(clk), .in(cmc_strb_sa), .out(cmc_strb_sa_b));
assign mb_out = cmc_strb_sa_b ? core[cma] : 0;
wire [0:35] corescope;
assign corescope = core[cma];
always @(posedge clk) begin
if(cmc_power_start)
cmc_aw_rq <= 1;
if(cmc_aw_rq) begin
if(cmpc_p0_rq)
cmc_p0_act <= 1;
else if(cmpc_p1_rq)
cmc_p1_act <= 1;
else if(cmpc_p2_rq) begin
if(~cmpc_p3_rq | cmc_last_proc)
cmc_p2_act <= 1;
end else if(cmpc_p3_rq) begin
if(~cmpc_p2_rq | ~cmc_last_proc)
cmc_p3_act <= 1;
end
end
if(cmc_state_clr) begin
cmc_p0_act <= 0;
cmc_p1_act <= 0;
cmc_p2_act <= 0;
cmc_p3_act <= 0;
end
if(cmc_t0) begin
cmc_aw_rq <= 0;
cmc_proc_rs <= 0;
cmc_pse_sync <= 0;
cmc_stop <= 0;
cma <= 0;
cma_rd_rq <= 0;
cma_wr_rq <= 0;
end
if(cmc_t1) begin
cma <= cma | ma_p0[22:35];
if(mc_rd_rq)
cma_rd_rq <= 1;
if(mc_wr_rq)
cma_wr_rq <= 1;
end
if(cmc_t2) begin
cmc_rd <= 1;
if(cmc_p2_act)
cmc_last_proc <= 0;
if(cmc_p3_act)
cmc_last_proc <= 1;
end
if(cmc_t5) begin
// this is hack, normally core should be cleared
// roughly at the time of cmc_strb_sa, which is
// however does not happen on a write
core[cma] <= 0;
cmc_rd <= 0;
cmc_pse_sync <= 1;
end
if(cmc_t7)
cmc_inhibit <= 1; // totally useless
if(cmc_t8)
cmc_wr <= 1;
if(cmc_t9 & cmc_wr)
// again a hack, core is written some time after T8
// ...and we know cmc_wr is set then anway.
core[cma] <= core[cma] | cmb;
if(cmc_t11)
cmc_aw_rq <= 1;
if(cmc_t12) begin
cmc_rd <= 0;
cmc_wr <= 0;
cmc_inhibit <= 0;
end
if(mc_wr_rs_S)
cmc_proc_rs <= 1;
if(cmc_strb_sa) begin
cmb <= mb_out;
end
if(cmc_cmb_clr)
cmb <= 0;
if(mb_pulse)
cmb <= cmb | mb_in;
end
endmodule

234
verilog/fast162.v Normal file
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@@ -0,0 +1,234 @@
module fast162(
input wire clk,
input wire reset,
input wire power,
input wire sw_single_step,
input wire sw_restart,
input wire membus_wr_rs_p0,
input wire membus_rq_cyc_p0,
input wire membus_rd_rq_p0,
input wire membus_wr_rq_p0,
input wire [21:35] membus_ma_p0,
input wire [18:21] membus_sel_p0,
input wire membus_fmc_select_p0,
input wire [0:35] membus_mb_in_p0,
output wire membus_addr_ack_p0,
output wire membus_rd_rs_p0,
output wire [0:35] membus_mb_out_p0,
input wire membus_wr_rs_p1,
input wire membus_rq_cyc_p1,
input wire membus_rd_rq_p1,
input wire membus_wr_rq_p1,
input wire [21:35] membus_ma_p1,
input wire [18:21] membus_sel_p1,
input wire membus_fmc_select_p1,
input wire [0:35] membus_mb_in_p1,
output wire membus_addr_ack_p1,
output wire membus_rd_rs_p1,
output wire [0:35] membus_mb_out_p1,
input wire membus_wr_rs_p2,
input wire membus_rq_cyc_p2,
input wire membus_rd_rq_p2,
input wire membus_wr_rq_p2,
input wire [21:35] membus_ma_p2,
input wire [18:21] membus_sel_p2,
input wire membus_fmc_select_p2,
input wire [0:35] membus_mb_in_p2,
output wire membus_addr_ack_p2,
output wire membus_rd_rs_p2,
output wire [0:35] membus_mb_out_p2,
input wire membus_wr_rs_p3,
input wire membus_rq_cyc_p3,
input wire membus_rd_rq_p3,
input wire membus_wr_rq_p3,
input wire [21:35] membus_ma_p3,
input wire [18:21] membus_sel_p3,
input wire membus_fmc_select_p3,
input wire [0:35] membus_mb_in_p3,
output wire membus_addr_ack_p3,
output wire membus_rd_rs_p3,
output wire [0:35] membus_mb_out_p3
);
/* Jumpers */
reg [0:3] memsel_p0;
reg [0:3] memsel_p1;
reg [0:3] memsel_p2;
reg [0:3] memsel_p3;
reg fmc_p0_sel;
reg fmc_p1_sel;
reg fmc_p2_sel;
reg fmc_p3_sel;
reg fmc_act;
reg fmc_rd0;
reg fmc_rs;
reg fmc_stop;
reg fmc_wr;
wire [0:35] fm_out = (fma != 0 | fmc_rd0) ? ff[fma] : 0;
reg [0:35] ff[0:16];
wire wr_rs = fmc_p0_sel ? membus_wr_rs_p0 :
fmc_p1_sel ? membus_wr_rs_p1 :
fmc_p2_sel ? membus_wr_rs_p2 :
fmc_p3_sel ? membus_wr_rs_p3 : 0;
wire rq_cyc = fmc_p0_sel ? membus_rq_cyc_p0 :
fmc_p1_sel ? membus_rq_cyc_p1 :
fmc_p2_sel ? membus_rq_cyc_p2 :
fmc_p3_sel ? membus_rq_cyc_p3 : 0;
wire fma_rd_rq = fmc_p0_sel ? membus_rd_rq_p0 :
fmc_p1_sel ? membus_rd_rq_p1 :
fmc_p2_sel ? membus_rd_rq_p2 :
fmc_p3_sel ? membus_rd_rq_p3 : 0;
wire fma_wr_rq = fmc_p0_sel ? membus_wr_rq_p0 :
fmc_p1_sel ? membus_wr_rq_p1 :
fmc_p2_sel ? membus_wr_rq_p2 :
fmc_p3_sel ? membus_wr_rq_p3 : 0;
wire [21:35] fma = fmc_p0_sel ? membus_ma_p0[32:35] :
fmc_p1_sel ? membus_ma_p1[32:35] :
fmc_p2_sel ? membus_ma_p2[32:35] :
fmc_p3_sel ? membus_ma_p3[32:35] : 0;
wire [0:35] mb_in = fmc_p0_sel ? membus_mb_in_p0 :
fmc_p1_sel ? membus_mb_in_p1 :
fmc_p2_sel ? membus_mb_in_p2 :
fmc_p3_sel ? membus_mb_in_p3 : 0;
assign membus_addr_ack_p0 = fmc_addr_ack & fmc_p0_sel;
assign membus_rd_rs_p0 = fmc_rd_rs & fmc_p0_sel;
assign membus_mb_out_p0 = fmc_p0_sel ? mb_out : 0;
assign membus_addr_ack_p1 = fmc_addr_ack & fmc_p1_sel;
assign membus_rd_rs_p1 = fmc_rd_rs & fmc_p1_sel;
assign membus_mb_out_p1 = fmc_p1_sel ? mb_out : 0;
assign membus_addr_ack_p2 = fmc_addr_ack & fmc_p2_sel;
assign membus_rd_rs_p2 = fmc_rd_rs & fmc_p2_sel;
assign membus_mb_out_p2 = fmc_p2_sel ? mb_out : 0;
assign membus_addr_ack_p3 = fmc_addr_ack & fmc_p3_sel;
assign membus_rd_rs_p3 = fmc_rd_rs & fmc_p3_sel;
assign membus_mb_out_p3 = fmc_p3_sel ? mb_out : 0;
wire fmc_addr_ack;
wire fmc_rd_rs;
wire [0:35] mb_out = fmc_rd_strb ? fm_out : 0;
wire fmc_p0_sel1 = fmc_p0_sel & ~fmc_stop;
wire fmc_p1_sel1 = fmc_p1_sel & ~fmc_stop;
wire fmc_p2_sel1 = fmc_p2_sel & ~fmc_stop;
wire fmc_p3_sel1 = fmc_p3_sel & ~fmc_stop;
wire fmc_p0_wr_sel = fmc_p0_sel & fmc_act & ~fma_rd_rq;
wire fmc_p1_wr_sel = fmc_p1_sel & fmc_act & ~fma_rd_rq;
wire fmc_p2_wr_sel = fmc_p2_sel & fmc_act & ~fma_rd_rq;
wire fmc_p3_wr_sel = fmc_p3_sel & fmc_act & ~fma_rd_rq;
wire fmpc_p0_rq = fmc_p0_sel1 & memsel_p0 == membus_sel_p0 &
membus_fmc_select_p0 & membus_rq_cyc_p0;
wire fmpc_p1_rq = fmc_p1_sel1 & memsel_p1 == membus_sel_p1 &
membus_fmc_select_p1 & membus_rq_cyc_p1;
wire fmpc_p2_rq = fmc_p2_sel1 & memsel_p2 == membus_sel_p2 &
membus_fmc_select_p2 & membus_rq_cyc_p2;
wire fmpc_p3_rq = fmc_p3_sel1 & memsel_p3 == membus_sel_p3 &
membus_fmc_select_p3 & membus_rq_cyc_p3;
wire fmc_pwr_on;
wire fmc_restart;
wire fmc_start;
wire fmc_rd_strb;
wire fmct0;
wire fmct1;
wire fmct3;
wire fmct4;
wire fmct5;
wire fm_clr;
wire fmc_wr_set;
wire fmc_wr_rs;
wire fma_rd_rq_P, fma_rd_rq_D, fmc_rd0_set;
wire fmct1_D, fmct3_D;
wire mb_pulse_in;
pg fmc_pg0(.clk(clk), .reset(reset), .in(power), .p(fmc_pwr_on));
pg fmc_pg1(.clk(clk), .reset(reset), .in(sw_restart & fmc_stop),
.p(fmc_restart));
pg fmc_pg2(.clk(clk), .reset(reset), .in(fmc_act), .p(fmct0));
pg fmc_pg3(.clk(clk), .reset(reset), .in(fma_rd_rq), .p(fma_rd_rq_P));
pg cmc_pg4(.clk(clk), .reset(reset), .in(| mb_in), .p(mb_pulse_in));
pg cmc_pg5(.clk(clk), .reset(reset), .in(wr_rs), .p(fmc_wr_rs));
pa fmc_pa0(.clk(clk), .reset(reset),
.in(fmc_start | fmct4 & ~fmc_stop),
.p(fmct5));
pa fmc_pa1(.clk(clk), .reset(reset),
.in(fmct0 & fma_rd_rq),
.p(fmct1));
pa fmc_pa2(.clk(clk), .reset(reset),
.in(fma_rd_rq_D),
.p(fmc_rd0_set));
pa fmc_pa3(.clk(clk), .reset(reset),
.in(fmct3),
.p(fm_clr));
pa fmc_pa4(.clk(clk), .reset(reset),
.in(fmct3_D),
.p(fmc_wr_set));
pg fmc_pg5(.clk(clk), .reset(reset),
.in(fmct0 & ~fma_rd_rq & fma_wr_rq |
fmct1_D & fma_wr_rq),
.p(fmct3));
pa fmc_pa6(.clk(clk), .reset(reset),
.in(fmct1_D & ~fma_wr_rq | fmc_wr_rs),
.p(fmct4));
dly200ns fmc_dly0(.clk(clk), .reset(reset),
.in(fmc_restart | fmc_pwr_on),
.p(fmc_start));
dly50ns fmc_dly1(.clk(clk), .reset(reset),
.in(fma_rd_rq_P),
.p(fma_rd_rq_D));
dly100ns fmc_dly3(.clk(clk), .reset(reset),
.in(fmct1),
.p(fmct1_D));
dly50ns fmc_dly4(.clk(clk), .reset(reset),
.in(fmct3),
.p(fmct3_D));
bd fmc_bd0(.clk(clk), .reset(reset), .in(fmct0), .p(fmc_addr_ack));
bd fmc_bd1(.clk(clk), .reset(reset), .in(fmct1), .p(fmc_rd_rs));
bd2 fmc_bd2(.clk(clk), .reset(reset), .in(fmct1), .p(fmc_rd_strb));
always @(posedge reset) begin
fmc_act <= 0;
end
always @(posedge clk) begin
if(fmc_restart | fmc_pwr_on) begin
fmc_act <= 0;
fmc_stop <= 1;
end
if(fmpc_p0_rq | fmpc_p1_rq | fmpc_p2_rq | fmpc_p3_rq)
fmc_act <= 1;
if(fmc_wr_rs)
fmc_rs <= 1;
if(~fma_rd_rq)
fmc_rd0 <= 0;
if(fmc_rd0_set)
fmc_rd0 <= 1;
if(fmc_wr_set)
fmc_wr <= 1;
if(fm_clr)
ff[fma] <= 0;
if(mb_pulse_in & fmc_wr)
ff[fma] <= ff[fma] | mb_in;
if(fmct0) begin
fmc_rs <= 0;
fmc_stop <= sw_single_step;
end
if(fmct4) begin
fmc_act <= 0;
fmc_rd0 <= 0;
end
if(fmct5) begin
fmc_stop <= 0;
fmc_wr <= 0;
end
end
endmodule

195
verilog/fastmem.v
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@@ -1,195 +0,0 @@
module fastmem(
input clk,
input mc_wr_rs_p0,
input mc_rq_cyc_p0,
input mc_rd_rq_p0,
input mc_wr_rq_p0,
input [21:35] ma_p0,
input [18:21] sel_p0,
input fmc_select_p0,
input [0:35] mb_in_p0,
output cmc_addr_ack_p0,
output cmc_rd_rs_p0,
output [0:35] mb_out_p0,
input mc_wr_rs_p1,
input mc_rq_cyc_p1,
input mc_rd_rq_p1,
input mc_wr_rq_p1,
input [21:35] ma_p1,
input [18:21] sel_p1,
input fmc_select_p1,
input [0:35] mb_in_p1,
output cmc_addr_ack_p1,
output cmc_rd_rs_p1,
output [0:35] mb_out_p1,
input mc_wr_rs_p2,
input mc_rq_cyc_p2,
input mc_rd_rq_p2,
input mc_wr_rq_p2,
input [21:35] ma_p2,
input [18:21] sel_p2,
input fmc_select_p2,
input [0:35] mb_in_p2,
output cmc_addr_ack_p2,
output cmc_rd_rs_p2,
output [0:35] mb_out_p2,
input mc_wr_rs_p3,
input mc_rq_cyc_p3,
input mc_rd_rq_p3,
input mc_wr_rq_p3,
input [21:35] ma_p3,
input [18:21] sel_p3,
input fmc_select_p3,
input [0:35] mb_in_p3,
output cmc_addr_ack_p3,
output cmc_rd_rs_p3,
output [0:35] mb_out_p3
);
wire [0:35] mb_out;
wire [0:35] mb_in;
reg power;
reg single_step_sw;
reg restart_sw;
reg [0:3] memsel_p0;
reg [0:3] memsel_p1;
reg [0:3] memsel_p2;
reg [0:3] memsel_p3;
reg fmc_p0_sel;
reg fmc_p1_sel;
reg fmc_p2_sel;
reg fmc_p3_sel;
reg fmc_act, fmc_rd0, fmc_rs, fmc_stop, fmc_wr;
reg [0:35] ff[0:16];
wire [32:35] fma;
wire fma_rd_rq, fma_wr_rq;
wire [0:35] fm_out;
// simulate power on
initial begin
power = 0;
single_step_sw = 0;
restart_sw = 0;
#500 power = 1;
end
assign fma = fmc_p0_sel ? ma_p0[32:35] :
fmc_p1_sel ? ma_p1[32:35] :
fmc_p2_sel ? ma_p2[32:35] :
fmc_p3_sel ? ma_p3[32:35] : 0;
assign mb_in = fmc_p0_sel ? mb_in_p0 :
fmc_p1_sel ? mb_in_p1 :
fmc_p2_sel ? mb_in_p2 :
fmc_p3_sel ? mb_in_p3 : 0;
assign fmc_wr_rs = fmc_p0_sel ? mc_wr_rs_p0 :
fmc_p1_sel ? mc_wr_rs_p1 :
fmc_p2_sel ? mc_wr_rs_p2 :
fmc_p3_sel ? mc_wr_rs_p3 : 0;
assign fma_rd_rq = fmc_p0_sel ? mc_rd_rq_p0 :
fmc_p1_sel ? mc_rd_rq_p1 :
fmc_p2_sel ? mc_rd_rq_p2 :
fmc_p3_sel ? mc_rd_rq_p3 : 0;
assign fma_wr_rq = fmc_p0_sel ? mc_wr_rq_p0 :
fmc_p1_sel ? mc_wr_rq_p1 :
fmc_p2_sel ? mc_wr_rq_p2 :
fmc_p3_sel ? mc_wr_rq_p3 : 0;
assign cmc_addr_ack_p0 = fmc_addr_ack & fmc_p0_sel;
assign cmc_rd_rs_p0 = fmc_rd_rs & fmc_p0_sel;
assign mb_out_p0 = fmc_p0_sel ? mb_out : 0;
assign cmc_addr_ack_p1 = fmc_addr_ack & fmc_p1_sel;
assign cmc_rd_rs_p1 = fmc_rd_rs & fmc_p1_sel;
assign mb_out_p1 = fmc_p1_sel ? mb_out : 0;
assign cmc_addr_ack_p2 = fmc_addr_ack & fmc_p2_sel;
assign cmc_rd_rs_p2 = fmc_rd_rs & fmc_p2_sel;
assign mb_out_p2 = fmc_p2_sel ? mb_out : 0;
assign cmc_addr_ack_p3 = fmc_addr_ack & fmc_p3_sel;
assign cmc_rd_rs_p3 = fmc_rd_rs & fmc_p3_sel;
assign mb_out_p3 = fmc_p3_sel ? mb_out : 0;
assign fmc_addr_ack = fmc_t0;
assign fmc_rd_rs = fmc_t1;
assign mb_out = fmc_rd_strb ? fm_out : 0;
assign fm_out = fma > 0 | fmc_rd0 ? ff[fma] : 0;
assign fmc_p0_sel1 = fmc_p0_sel & ~fmc_stop;
assign fmc_p1_sel1 = fmc_p1_sel & ~fmc_stop;
assign fmc_p2_sel1 = fmc_p2_sel & ~fmc_stop;
assign fmc_p3_sel1 = fmc_p3_sel & ~fmc_stop;
assign fmc_p0_wr_sel = fmc_p0_sel & fmc_act & ~fma_rd_rq;
assign fmc_p1_wr_sel = fmc_p1_sel & fmc_act & ~fma_rd_rq;
assign fmc_p2_wr_sel = fmc_p2_sel & fmc_act & ~fma_rd_rq;
assign fmc_p3_wr_sel = fmc_p3_sel & fmc_act & ~fma_rd_rq;
assign fmpc_p0_rq = fmc_p0_sel1 & memsel_p0 == sel_p0 &
fmc_select_p0 & mc_rq_cyc_p0;
assign fmpc_p1_rq = fmc_p1_sel1 & memsel_p1 == sel_p1 &
fmc_select_p1 & mc_rq_cyc_p1;
assign fmpc_p2_rq = fmc_p2_sel1 & memsel_p2 == sel_p2 &
fmc_select_p2 & mc_rq_cyc_p2;
assign fmpc_p3_rq = fmc_p3_sel1 & memsel_p3 == sel_p3 &
fmc_select_p3 & mc_rq_cyc_p3;
// Pulses
// the delays here aren't accurate, but gate delays accumulate
syncpulse syncfmc0(.clk(clk), .in(power), .out(fmc_pwr_start));
syncpulse syncfmc1(.clk(clk), .in(fma_rd_rq), .out(fma_rd_rqD));
dly50ns fmcdly0(.clk(clk), .in(fma_rd_rqD), .out(fmc_rd0_set));
syncpulse syncfmc2(.clk(clk), .in(fmc_act), .out(fmc_t0));
dly50ns fmcdly1(.clk(clk), .in(fmc_t0), .out(fmc_t0D));
assign fmc_t1 = fmc_t0D & fma_rd_rq;
// generate a longer pulse so processor has time to read
pa100ns fmcpa0(.clk(clk), .in(fmc_t1), .out(fmc_rd_strb));
dly100ns fmcdly2(.clk(clk), .in(fmc_t1), .out(fmc_t1D));
assign fmc_t3 = fmc_t0D & ~fma_rd_rq & fma_wr_rq |
fmc_t1D & fma_wr_rq;
assign fmc_restart = fmc_pwr_start;
dly200ns fmcdly3(.clk(clk), .in(fmc_restart), .out(fmc_start), .level(fmc_clr));
assign fmc_t4 = fmc_wr_rsD | fmc_t1D & ~fma_wr_rq;
dly50ns fmcdly4(.clk(clk), .in(fmc_t4), .out(fmc_t4D));
assign fmc_t5 = fmc_start | fmc_t4D & ~fmc_stop;
syncpulse syncfmc3(.clk(clk), .in(| mb_in), .out(fmb_in));
syncpulse syncfmc4(.clk(clk), .in(fmc_wr_rs), .out(fmc_wr_rsS));
dly50ns fmcdly5(.clk(clk), .in(fmc_wr_rsS), .out(fmc_wr_rsD));
wire [0:35] wordn;
assign wordn = ff[fma];
always @(posedge clk) begin
if(fmc_clr) begin
fmc_act <= 0;
fmc_stop <= 1;
end
if(fmpc_p0_rq | fmpc_p1_rq | fmpc_p2_rq | fmpc_p3_rq)
fmc_act <= 1;
if(fmc_rd0_set)
fmc_rd0 <= 1;
if(~fma_rd_rq)
fmc_rd0 <= 0;
if(fmc_t0) begin
fmc_rs <= 0;
fmc_stop <= single_step_sw;
end
if(fmc_t3) begin
fmc_wr <= 1;
ff[fma] <= 0;
end
if(fmc_t4) begin
fmc_rd0 <= 0;
fmc_act <= 0;
end
if(fmc_t5) begin
fmc_stop <= 0;
fmc_wr <= 0;
end
if(fmb_in & fmc_wr)
ff[fma] <= ff[fma] | mb_in;
if(fmc_wr_rsS)
fmc_rs <= 1;
end
endmodule

362
verilog/modules.v
View File

@@ -1,173 +1,209 @@
module syncpulse(
module pg(
input clk,
input reset,
input in,
output out
output p
);
reg x0, x1;
initial begin
x0 <= 0;
x1 <= 0;
end
always @(posedge clk) begin
x0 <= in;
x1 <= x0;
end
assign out = x0 && !x1;
reg [1:0] x;
always @(posedge clk or posedge reset)
if(reset)
x <= 0;
else
x <= { x[0], in };
assign p = x[0] & !x[1];
endmodule
module sbr(
input clk,
input clr,
input set,
input from,
output ret
);
reg ff;
always @(posedge clk) begin
if(clr | from)
ff <= 0;
if(set)
ff <= 1;
end
assign ret = ff & from;
module pa(input clk, input reset, input in, output p);
reg p;
always @(posedge clk or posedge reset)
if(reset)
p <= 0;
else
p <= in;
endmodule
module pa100ns(
input clk,
input in,
output out
);
reg [1:0] r;
initial
r <= 0;
always @(posedge clk) begin
r = r << 1;
if(in)
r = 4'b11;
end
assign out = r[1];
endmodule
module dly50ns(
input clk,
input in,
output out
);
reg r;
initial
r <= 0;
always @(posedge clk)
r <= {r, in};
assign out = r;
endmodule
module dly100ns(
input clk,
input in,
output out
);
reg [1:0] r;
initial
r <= 0;
always @(posedge clk)
r <= {r, in};
assign out = r[1];
endmodule
module dly150ns(
input clk,
input in,
output out
);
reg [2:0] r;
initial
r <= 0;
always @(posedge clk)
r <= {r, in};
assign out = r[2];
endmodule
module dly200ns(
input clk,
input in,
output out,
output level
);
/*
module pa100ns(input clk, input reset, input in, output p);
reg [3:0] r;
initial
r <= 0;
always @(posedge clk)
r <= {r, in};
assign out = r[3];
assign level = (|r[2:0]);
endmodule
module dly250ns(
input clk,
input in,
output out
);
reg [4:0] r;
initial
r <= 0;
always @(posedge clk)
r <= {r, in};
assign out = r[4];
endmodule
module dly400ns(
input clk,
input in,
output out
);
reg [7:0] r;
initial
r <= 0;
always @(posedge clk)
r <= {r, in};
assign out = r[7];
endmodule
module dly800ns(
input clk,
input in,
output out
);
reg [15:0] r;
initial
r <= 0;
always @(posedge clk)
r <= {r, in};
assign out = r[15];
endmodule
module dly1000ns(
input clk,
input in,
output out
);
reg [19:0] r;
initial
r <= 0;
always @(posedge clk)
r <= {r, in};
assign out = r[19];
endmodule
module dly100us(
input clk,
input in,
output out
);
reg [15:0] r;
initial
r <= 0;
always @(posedge clk) begin
if(r)
r = r + 1;
if(in)
r = 1;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 1;
if(in)
r <= 1;
end
end
assign out = r == 2000;
assign p = r && r <= 10;
endmodule
*/
/* "bus driver", 40ns delayed pulse */
module bd(input clk, input reset, input in, output p);
reg [2:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 1;
if(in)
r <= 1;
end
end
assign p = r == 4;
endmodule
/* Same as above but with longer pulse. Used to pulse mb
* because one more clock cycle is needed to get the data
* after the pulse has been synchronizes. */
module bd2(input clk, input reset, input in, output p);
reg [2:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 1;
if(in)
r <= 1;
end
end
assign p = r == 4 || r == 5;
endmodule
module dly50ns(input clk, input reset, input in, output p);
reg [2:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 1;
if(in)
r <= 1;
end
end
assign p = r == 7;
endmodule
module dly100ns(input clk, input reset, input in, output p);
reg [3:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 1;
if(in)
r <= 1;
end
end
assign p = r == 12;
endmodule
module dly150ns(input clk, input reset, input in, output p);
reg [4:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 1;
if(in)
r <= 1;
end
end
assign p = r == 17;
endmodule
module dly200ns(input clk, input reset, input in, output p);
reg [4:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 1;
if(in)
r <= 1;
end
end
assign p = r == 22;
endmodule
module dly250ns(input clk, input reset, input in, output p);
reg [4:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 1;
if(in)
r <= 1;
end
end
assign p = r == 27;
endmodule
module dly400ns(input clk, input reset, input in, output p);
reg [5:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 1;
if(in)
r <= 1;
end
end
assign p = r == 42;
endmodule
module dly800ns(input clk, input reset, input in, output p);
reg [6:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 1;
if(in)
r <= 1;
end
end
assign p = r == 82;
endmodule
module dly1us(input clk, input reset, input in, output p);
reg [6:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 1;
if(in)
r <= 1;
end
end
assign p = r == 102;
endmodule
module dly100us(input clk, input reset, input in, output p);
reg [15:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 1;
if(in)
r <= 1;
end
end
assign p = r == 10002;
endmodule

244
verilog/pdp6.v Normal file
View File

@@ -0,0 +1,244 @@
`default_nettype none
module pdp6(
input wire clk,
input wire reset
);
// keys
reg key_start;
reg key_read_in;
reg key_mem_cont;
reg key_inst_cont;
reg key_mem_stop;
reg key_inst_stop;
reg key_exec;
reg key_io_reset;
reg key_dep;
reg key_dep_nxt;
reg key_ex;
reg key_ex_nxt;
// switches
reg sw_addr_stop;
reg sw_mem_disable;
reg sw_repeat;
reg sw_power;
reg [0:35] datasw;
reg [18:35] mas;
// maintenance switches
reg sw_rim_maint;
reg sw_repeat_bypass;
reg sw_art3_maint;
reg sw_sct_maint;
reg sw_split_cyc;
// lights
wire [0:17] ir;
wire [0:35] mi;
wire [0:35] ar;
wire [0:35] mb;
wire [0:35] mq;
wire [18:35] pc;
wire [18:35] ma;
wire [0:8] fe;
wire [0:8] sc;
wire run;
wire mc_stop;
wire pi_active;
wire [1:7] pih;
wire [1:7] pir;
wire [1:7] pio;
wire [18:25] pr;
wire [18:25] rlr;
wire [18:25] rla;
/* Mem bus */
wire membus_wr_rs_p0;
wire membus_rq_cyc_p0;
wire membus_rd_rq_p0;
wire membus_wr_rq_p0;
wire [21:35] membus_ma_p0;
wire [18:21] membus_sel_p0;
wire membus_fmc_select_p0;
wire membus_addr_ack_p0;
wire membus_rd_rs_p0;
wire [0:35] membus_mb_in_p0;
/* Out of apr0 */
wire [0:35] membus_mb_out_p0_p;
/* Out of fmem0 */
wire [0:35] membus_mb_out_p0_0;
wire membus_addr_ack_p0_0;
wire membus_rd_rs_p0_0;
/* Out of mem0 */
wire [0:35] membus_mb_out_p0_1;
wire membus_addr_ack_p0_1;
wire membus_rd_rs_p0_1;
/* IO bus */
wire iobus_iob_poweron;
wire iobus_iob_reset;
wire iobus_datao_clear;
wire iobus_datao_set;
wire iobus_cono_clear;
wire iobus_cono_set;
wire iobus_iob_fm_datai;
wire iobus_iob_fm_status;
wire [3:9] iobus_ios;
wire [0:35] iobus_iob_out;
wire [1:7] iobus_pi_req;
wire [0:35] iobus_iob_in;
assign membus_mb_in_p0 = membus_mb_out_p0_p | membus_mb_out_p0_0 | membus_mb_out_p0_1;
assign membus_addr_ack_p0 = membus_addr_ack_p0_0 | membus_addr_ack_p0_1;
assign membus_rd_rs_p0 = membus_rd_rs_p0_0 | membus_rd_rs_p0_1;
apr apr0(
.clk(clk),
.reset(reset),
.key_start(key_start),
.key_read_in(key_read_in),
.key_mem_cont(key_mem_cont),
.key_inst_cont(key_inst_cont),
.key_mem_stop(key_mem_stop),
.key_inst_stop(key_inst_stop),
.key_exec(key_exec),
.key_io_reset(key_io_reset),
.key_dep(key_dep),
.key_dep_nxt(key_dep_nxt),
.key_ex(key_ex),
.key_ex_nxt(key_ex_nxt),
.sw_addr_stop(sw_addr_stop),
.sw_mem_disable(sw_mem_disable),
.sw_repeat(sw_repeat),
.sw_power(sw_power),
.datasw(datasw),
.mas(mas),
.sw_rim_maint(sw_rim_maint),
.sw_repeat_bypass(sw_repeat_bypass),
.sw_art3_maint(sw_art3_maint),
.sw_sct_maint(sw_sct_maint),
.sw_split_cyc(sw_split_cyc),
.ir(ir),
.mi(mi),
.ar(ar),
.mb(mb),
.mq(mq),
.pc(pc),
.ma(ma),
.fe(fe),
.sc(sc),
.run(run),
.mc_stop(mc_stop),
.pi_active(pi_active),
.pih(pih),
.pir(pir),
.pio(pio),
.pr(pr),
.rlr(rlr),
.rla(rla),
.membus_wr_rs(membus_wr_rs_p0),
.membus_rq_cyc(membus_rq_cyc_p0),
.membus_rd_rq(membus_rd_rq_p0),
.membus_wr_rq(membus_wr_rq_p0),
.membus_ma(membus_ma_p0),
.membus_sel(membus_sel_p0),
.membus_fmc_select(membus_fmc_select_p0),
.membus_mb_out(membus_mb_out_p0_p),
.membus_addr_ack(membus_addr_ack_p0),
.membus_rd_rs(membus_rd_rs_p0),
.membus_mb_in(membus_mb_in_p0),
.iobus_iob_poweron(iobus_iob_poweron),
.iobus_iob_reset(iobus_iob_reset),
.iobus_datao_clear(iobus_datao_clear),
.iobus_datao_set(iobus_datao_set),
.iobus_cono_clear(iobus_cono_clear),
.iobus_cono_set(iobus_cono_set),
.iobus_iob_fm_datai(iobus_iob_fm_datai),
.iobus_iob_fm_status(iobus_iob_fm_status),
.iobus_ios(iobus_ios),
.iobus_iob_out(iobus_iob_out),
.iobus_pi_req(iobus_pi_req),
.iobus_iob_in(iobus_iob_in)
);
reg mem0_sw_single_step;
reg mem0_sw_restart;
fast162 fmem0(
.clk(clk),
.reset(reset),
.power(sw_power),
.sw_single_step(mem0_sw_single_step),
.sw_restart(mem0_sw_restart),
.membus_wr_rs_p0(membus_wr_rs_p0),
.membus_rq_cyc_p0(membus_rq_cyc_p0),
.membus_rd_rq_p0(membus_rd_rq_p0),
.membus_wr_rq_p0(membus_wr_rq_p0),
.membus_ma_p0(membus_ma_p0),
.membus_sel_p0(membus_sel_p0),
.membus_fmc_select_p0(membus_fmc_select_p0),
.membus_mb_in_p0(membus_mb_in_p0),
.membus_addr_ack_p0(membus_addr_ack_p0_0),
.membus_rd_rs_p0(membus_rd_rs_p0_0),
.membus_mb_out_p0(membus_mb_out_p0_0),
.membus_rq_cyc_p1(1'b0),
.membus_sel_p1(4'b0),
.membus_fmc_select_p1(1'b0),
.membus_rq_cyc_p2(1'b0),
.membus_sel_p2(4'b0),
.membus_fmc_select_p2(1'b0),
.membus_rq_cyc_p3(1'b0),
.membus_sel_p3(4'b0),
.membus_fmc_select_p3(1'b0)
);
core161c mem0(
.clk(clk),
.reset(reset),
.power(sw_power),
.sw_single_step(mem0_sw_single_step),
.sw_restart(mem0_sw_restart),
.membus_wr_rs_p0(membus_wr_rs_p0),
.membus_rq_cyc_p0(membus_rq_cyc_p0),
.membus_rd_rq_p0(membus_rd_rq_p0),
.membus_wr_rq_p0(membus_wr_rq_p0),
.membus_ma_p0(membus_ma_p0),
.membus_sel_p0(membus_sel_p0),
.membus_fmc_select_p0(membus_fmc_select_p0),
.membus_mb_in_p0(membus_mb_in_p0),
.membus_addr_ack_p0(membus_addr_ack_p0_1),
.membus_rd_rs_p0(membus_rd_rs_p0_1),
.membus_mb_out_p0(membus_mb_out_p0_1),
.membus_rq_cyc_p1(1'b0),
.membus_sel_p1(4'b0),
.membus_fmc_select_p1(1'b0),
.membus_rq_cyc_p2(1'b0),
.membus_sel_p2(4'b0),
.membus_fmc_select_p2(1'b0),
.membus_rq_cyc_p3(1'b0),
.membus_sel_p3(4'b0),
.membus_fmc_select_p3(1'b0)
);
endmodule

491
verilog/test.gtkw
View File

@@ -1,303 +1,230 @@
[*]
[*] GTKWave Analyzer v3.3.76 (w)1999-2016 BSI
[*] Tue Nov 8 22:00:50 2016
[*] Sat Nov 12 18:37:06 2016
[*]
[dumpfile] "/home/aap/src/verilog/dump.vcd"
[dumpfile_mtime] "Tue Nov 8 19:25:18 2016"
[dumpfile_size] 49349
[savefile] "/home/aap/src/verilog/test.gtkw"
[timestart] 6847
[size] 1916 1071
[dumpfile] "/home/aap/src/pdp6/verilog/new/dump.vcd"
[dumpfile_mtime] "Sat Nov 12 18:36:40 2016"
[dumpfile_size] 98790
[savefile] "/home/aap/src/pdp6/verilog/new/test.gtkw"
[timestart] 0
[size] 1920 1080
[pos] -1 -1
*-9.999172 8463 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-9.650465 1200 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] test.
[treeopen] test.fmem0.
[sst_width] 240
[signals_width] 293
[treeopen] test.pdp6.
[treeopen] test.pdp6.mem0.
[sst_width] 337
[signals_width] 442
[sst_expanded] 1
[sst_vpaned_height] 286
[sst_vpaned_height] 319
@28
>-2
test.apr.clk
@800200
>0
-regs
@30
test.apr.ar[0:35]
test.apr.mb[0:35]
test.apr.pc[18:35]
test.apr.ma[18:35]
test.apr.mas[18:35]
test.apr.datasw[0:35]
test.apr.mi[0:35]
test.apr.rlr[18:25]
test.apr.rla[18:25]
@28
test.apr.pr18ok
test.apr.pr_rel_AND_ma_ok
test.apr.pr_rel_AND_NOT_ma_ok
@1000200
-regs
@800200
-general
@28
test.apr.run
test.apr.mr_clr
test.apr.mr_start
@1000200
-general
test.clk
test.reset
@c00200
-ma
-sw
@28
test.apr.ma_reg.key_ma_fm_masw1
test.apr.ma_reg.ma_clr
test.apr.ma_reg.ma_fm_pc1
test.apr.ma_reg.ma_inc
test.pdp6.apr0.sw_power
test.pdp6.apr0.sw_repeat
test.pdp6.apr0.sw_addr_stop
test.pdp6.apr0.sw_mem_disable
test.pdp6.apr0.sw_rim_maint
test.pdp6.apr0.sw_split_cyc
test.pdp6.apr0.sw_repeat_bypass
test.pdp6.apr0.sw_art3_maint
test.pdp6.apr0.sw_sct_maint
@1401200
-ma
@c00200
-pc
@28
test.apr.pc_clr
test.apr.pc_fm_ma1
test.apr.pc_inc
@1401200
-pc
@c00200
-mb
@28
test.apr.mblt_clr
test.apr.mbrt_clr
test.apr.mblt_fm_ar0
test.apr.mbrt_fm_ar0
test.apr.mblt_fm_ar1
test.apr.mbrt_fm_ar1
test.apr.mblt_fm_mbrtJ
test.apr.mbrt_fm_mbltJ
@1401200
-mb
@c00200
-ar
@28
test.apr.arlt_clr
test.apr.arrt_clr
test.apr.arlt_fm_mb0
test.apr.arrt_fm_mb0
test.apr.arlt_fm_mb1
test.apr.arrt_fm_mb1
test.apr.arlt_fm_datasw1
test.apr.arrt_fm_datasw1
@1401200
-ar
-sw
@c00200
-keys
@28
test.apr.key_start
test.apr.key_read_in
test.apr.key_mem_cont
test.apr.key_inst_cont
test.apr.key_mem_stop
test.apr.key_inst_stop
test.apr.key_exec
test.apr.key_ioreset
test.apr.key_dep
test.apr.key_dep_nxt
test.apr.key_ex
test.apr.key_ex_nxt
test.pdp6.key_start
test.pdp6.key_read_in
test.pdp6.key_mem_cont
test.pdp6.key_inst_cont
test.pdp6.key_mem_stop
test.pdp6.key_inst_stop
test.pdp6.key_exec
test.pdp6.key_io_reset
test.pdp6.key_dep
test.pdp6.key_dep_nxt
test.pdp6.key_ex
test.pdp6.key_ex_nxt
@1401200
-keys
@c00200
-keytime
@28
test.apr.kt0
test.apr.kt0a
test.apr.key_tmp1
test.apr.kt1
test.apr.kt2
test.apr.kt3
test.apr.kt4
test.apr.key_wr
test.apr.key_rd
test.apr.key_rdwr_ret
test.apr.key_go
@1401200
-keytime
@800200
-EX
@28
test.apr.ex_user
test.apr.ex_mode_sync
test.apr.ex_uuo_sync
test.apr.ex_pi_sync
test.apr.ex_ill_op
test.apr.ex_inh_rel
test.apr.ex_clr
@1000200
-EX
@800200
-MC
@28
test.apr.mc_rd_rq_pulse
test.apr.mc_wr_rq_pulse
test.apr.mc_rdwr_rq_pulse
test.apr.mc_rdwr_rs_pulse
test.apr.mc_rq_pulse
test.apr.mc_tmp4
test.apr.mc_tmp5
test.apr.mc_illeg_address
test.apr.mc_non_exist_mem
test.apr.mc_non_exist_mem_rst
test.apr.mc_non_exist_rd
test.apr.mc_addr_ack
test.apr.mc_wr_rs
test.apr.mc_rs_t0
test.apr.mc_rs_t1
test.apr.mc_rd
test.apr.mc_mb_membus_enable
test.apr.mc_wr
test.apr.mc_rq
test.apr.mc_stop
test.apr.mc_stop_sync
test.apr.mc_split_cyc_sync
test.apr.mc_mb_clr
@1000200
-MC
@800200
-membus
-regs
@30
test.apr.membus_ma[21:35]
test.apr.membus_sel[18:21]
@28
test.apr.membus_fmc_select
test.apr.membus_mc_rq_cyc
test.apr.membus_mc_rd_rq
test.apr.membus_mc_wr_rq
test.apr.mc_mb_membus_enable
test.apr.membus_mai_cmc_addr_ack
test.apr.membus_mai_cmc_rd_rs
test.apr.membus_mc_wr_rs
@30
test.apr.membus_mb_in[0:35]
test.apr.membus_mb_out[0:35]
@1000200
-membus
@c00200
-mem0
@c00030
test.mem0.ma[21:35]
@28
(0)test.mem0.ma[21:35]
(1)test.mem0.ma[21:35]
(2)test.mem0.ma[21:35]
(3)test.mem0.ma[21:35]
(4)test.mem0.ma[21:35]
(5)test.mem0.ma[21:35]
(6)test.mem0.ma[21:35]
(7)test.mem0.ma[21:35]
(8)test.mem0.ma[21:35]
(9)test.mem0.ma[21:35]
(10)test.mem0.ma[21:35]
(11)test.mem0.ma[21:35]
(12)test.mem0.ma[21:35]
(13)test.mem0.ma[21:35]
(14)test.mem0.ma[21:35]
@1401200
-group_end
@30
test.mem0.mb_in[0:35]
test.mem0.mc_rq_cyc
test.mem0.mc_rd_rq
test.mem0.mc_wr_rq
test.mem0.mc_wr_rs
test.mem0.mb_out[0:35]
@28
test.mem0.cmc_addr_ack
test.mem0.cmc_rd_rs
@30
test.mem0.cma[22:35]
test.mem0.cma_rd_rq
test.mem0.cma_wr_rq
test.mem0.cmb[0:35]
@28
test.mem0.cmc_p0_act
test.mem0.cmc_p1_act
test.mem0.cmc_p2_act
test.mem0.cmc_p3_act
test.mem0.cmc_last_proc
test.mem0.cmc_aw_rq
test.mem0.cmc_rd
test.mem0.cmc_wr
test.mem0.cmc_inhibit
test.mem0.cmc_pse_sync
test.mem0.cmc_proc_rs
test.mem0.cmc_pwr_start
test.mem0.mc_wr_rs
test.mem0.cmc_t0
test.mem0.cmc_t1
test.mem0.cmc_t2
test.mem0.cmc_t4
test.mem0.cmc_t5
test.mem0.cmc_t6
test.mem0.cmc_t7
test.mem0.cmc_t8
test.mem0.cmc_t9
test.mem0.cmc_t9a
test.mem0.cmc_t10
test.mem0.cmc_t11
test.mem0.cmc_t12
test.mem0.cmc_strb_sa
test.mem0.cmc_state_clr
test.mem0.cyc_rq_p0
test.mem0.cyc_rq_p1
test.mem0.cyc_rq_p2
test.mem0.cyc_rq_p3
test.mem0.cmpc_p0_rq
test.mem0.cmpc_p1_rq
test.mem0.cmpc_p2_rq
test.mem0.cmpc_p3_rq
@30
test.mem0.corescope[0:35]
@1401200
-mem0
@800200
-fmem0
@28
test.fmem0.fmc_wr_rsS
@22
test.fmem0.fma[32:35]
@28
test.fmem0.fma_rd_rq
test.fmem0.fma_wr_rq
test.fmem0.fmc_p0_wr_sel
test.fmem0.fmc_clr
test.fmem0.fmc_rd0
test.fmem0.fmc_t0
test.fmem0.fmc_t1
test.fmem0.fmc_rd_strb
test.fmem0.fmc_t3
test.fmem0.fmc_t4
test.fmem0.fmc_t5
test.fmem0.fmc_wr_rs
test.fmem0.fmc_pwr_start
test.fmem0.fmc_restart
test.fmem0.fmc_start
test.fmem0.fmc_act
test.fmem0.fmc_rd0
test.fmem0.fmc_rs
test.fmem0.fmc_stop
test.fmem0.fmc_wr
test.fmem0.fmpc_p0_rq
test.fmem0.fmpc_p1_rq
test.fmem0.fmpc_p2_rq
test.fmem0.fmpc_p3_rq
test.pdp6.apr0.ma[18:35]
test.pdp6.apr0.pc[18:35]
test.pdp6.apr0.ir[0:17]
test.pdp6.apr0.mb[0:35]
test.pdp6.apr0.ar[0:35]
test.pdp6.apr0.mq[0:35]
@31
test.fmem0.fm_out[0:35]
@28
test.fmem0.fmb_in
@30
test.fmem0.mb_in[0:35]
test.fmem0.wordn[0:35]
test.pdp6.apr0.datasw[0:35]
test.pdp6.apr0.mas[18:35]
@1000200
-fmem0
-regs
@c00200
-ex
@28
test.pdp6.apr0.ex_clr
test.pdp6.apr0.ex_user
test.pdp6.apr0.ex_inh_rel
@1401200
-ex
@c00200
-key
@28
test.pdp6.apr0.run
test.pdp6.apr0.key_rim_sbr
test.pdp6.apr0.key_rdwr
test.pdp6.apr0.mr_pwr_clr
test.pdp6.apr0.mr_start
test.pdp6.apr0.mr_clr
test.pdp6.apr0.key_dep_st
test.pdp6.apr0.key_ex_st
test.pdp6.apr0.key_ex_sync
test.pdp6.apr0.key_dep_sync
@200
-
@28
test.pdp6.apr0.key_ma_clr
test.pdp6.apr0.key_ma_fm_masw1
test.pdp6.apr0.key_ma_inc
test.pdp6.apr0.key_ar_clr
test.pdp6.apr0.key_ar_fm_datasw1
test.pdp6.apr0.key_rd
test.pdp6.apr0.key_wr
test.pdp6.apr0.kt0
test.pdp6.apr0.kt0a
test.pdp6.apr0.kt1
test.pdp6.apr0.kt2
test.pdp6.apr0.kt3
test.pdp6.apr0.kt4
test.pdp6.apr0.key_go
test.pdp6.apr0.key_rd
test.pdp6.apr0.key_wr
test.pdp6.apr0.key_rdwr_ret
@1401200
-key
@800200
-mc
@28
test.pdp6.apr0.mc_rd_rq_pulse
test.pdp6.apr0.mc_rdwr_rq_pulse
test.pdp6.apr0.mc_rdwr_rs_pulse
test.pdp6.apr0.mc_wr_rq_pulse
test.pdp6.apr0.mc_rq_pulse
test.pdp6.apr0.mc_mb_clr
test.pdp6.apr0.mc_rq_set
test.pdp6.apr0.mc_addr_ack
test.pdp6.apr0.mai_rd_rs
test.pdp6.apr0.mc_wr_rs
test.pdp6.apr0.mc_rs_t0
test.pdp6.apr0.mc_rs_t1
test.pdp6.apr0.mc_illeg_address
test.pdp6.apr0.mc_membus_fm_mb1
@200
-
@30
test.pdp6.apr0.rlr[18:25]
test.pdp6.apr0.rla[18:25]
test.pdp6.apr0.pr[18:25]
@28
test.pdp6.apr0.pr18_ok
@200
-
@28
test.pdp6.apr0.mc_rd
test.pdp6.apr0.mc_wr
test.pdp6.apr0.mc_rq
test.pdp6.apr0.mc_stop
test.pdp6.apr0.mc_stop_sync
test.pdp6.apr0.mc_split_cyc_sync
test.pdp6.apr0.mc_mb_membus_enable
@1000200
-mc
@c00200
-membus
@28
test.pdp6.apr0.membus_rq_cyc
test.pdp6.apr0.membus_rd_rq
test.pdp6.apr0.membus_wr_rq
test.pdp6.apr0.membus_wr_rs
@30
test.pdp6.apr0.membus_sel[18:21]
test.pdp6.apr0.membus_ma[21:35]
test.pdp6.apr0.membus_fmc_select
test.pdp6.apr0.membus_mb_out[0:35]
test.pdp6.apr0.membus_rd_rs
test.pdp6.apr0.membus_addr_ack
test.pdp6.apr0.membus_mb_in[0:35]
test.pdp6.apr0.mc_non_exist_mem
test.pdp6.apr0.mc_non_exist_mem_rst
test.pdp6.apr0.mc_non_exist_rd
@1401200
-membus
@c00200
-mem0
@28
test.pdp6.mem0.sw_single_step
test.pdp6.mem0.sw_restart
test.pdp6.mem0.cmc_key_restart
@200
-
@28
test.pdp6.mem0.cmc_await_rq
test.pdp6.mem0.cmc_rd
test.pdp6.mem0.cmc_inhibit
test.pdp6.mem0.cmc_wr
test.pdp6.mem0.cyc_rq_p0
test.pdp6.mem0.cyc_rq_p1
test.pdp6.mem0.cyc_rq_p2
test.pdp6.mem0.cyc_rq_p3
test.pdp6.mem0.cmc_p0_act
test.pdp6.mem0.cmc_p1_act
test.pdp6.mem0.cmc_p2_act
test.pdp6.mem0.cmc_p3_act
@30
test.pdp6.mem0.cmb[0:35]
@28
test.pdp6.apr0.membus_mb_pulse
@200
-
@30
test.pdp6.mem0.corescope[0:35]
test.pdp6.mem0.ma[21:35]
test.pdp6.mem0.cma[22:35]
@28
test.pdp6.mem0.cma_rd_rq
test.pdp6.mem0.cma_wr_rq
test.pdp6.mem0.cmc_pse_sync
test.pdp6.mem0.cmc_proc_rs
test.pdp6.mem0.cmc_proc_rs_P
@200
-
@28
test.pdp6.mem0.cmc_pwr_clr
test.pdp6.mem0.cmc_pwr_start
test.pdp6.mem0.cmc_state_clr
test.pdp6.mem0.cmc_cmb_clr
test.pdp6.mem0.cmc_strb_sa
test.pdp6.mem0.cmc_rd_rs
test.pdp6.mem0.cmc_t0
test.pdp6.mem0.cmc_t1
test.pdp6.mem0.cmc_t2
test.pdp6.mem0.cmc_t4
test.pdp6.mem0.cmc_t5
test.pdp6.mem0.cmc_t6
test.pdp6.mem0.cmc_t7
test.pdp6.mem0.cmc_t8
test.pdp6.mem0.cmc_t9
test.pdp6.mem0.cmc_t9a
test.pdp6.mem0.cmc_t10
test.pdp6.mem0.cmc_t11
test.pdp6.mem0.cmc_t12
@1401200
-mem0
[pattern_trace] 1
[pattern_trace] 0

286
verilog/test.v
View File

@@ -1,219 +1,121 @@
`timescale 1ns/1ns
module clock(
output clk
);
reg clk;
module clock(output reg clk);
initial
clk = 0;
always
#25 clk = ~clk;
initial
#20000 $finish;
// #150000 $finish;
#5 clk = ~clk;
endmodule
//`define TESTKEY key_start
//`define TESTKEY key_read_in
//`define TESTKEY key_ex_nxt
`define TESTKEY key_ex
//`define TESTKEY key_dep
//`define TESTKEY key_mem_cont
//`define TESTKEY pdp6.key_inst_stop
//`define TESTKEY pdp6.key_read_in
//`define TESTKEY pdp6.key_start
//`define TESTKEY pdp6.key_exec
`define TESTKEY pdp6.key_ex
//`define TESTKEY pdp6.key_dep
//`define TESTKEY pdp6.key_mem_cont
module test;
reg key_start, key_read_in;
reg key_inst_cont, key_mem_cont;
reg key_inst_stop, key_mem_stop;
reg key_exec, key_ioreset;
reg key_dep, key_dep_nxt;
reg key_ex, key_ex_nxt;
reg sw_addr_stop;
reg sw_mem_disable;
reg sw_repeat;
reg sw_power;
reg [18:35] mas;
reg [0:35] datasw;
reg sw_rim_maint;
wire clk;
reg reset;
wire [0:35] mi;
wire [21:35] ma_p0;
wire [18:21] sel_p0;
wire [0:35] mb_in_p0;
wire [0:35] mb_out_p0_p;
wire [0:35] mb_out_p0_0;
wire [0:35] mb_out_p0_1;
clock clock0(clk);
pdp6 pdp6(.clk(clk), .reset(reset));
clock clock(.clk(clk));
apr apr(
.clk(clk),
.key_start(key_start),
.key_read_in(key_read_in),
.key_inst_cont(key_inst_cont),
.key_mem_cont(key_mem_cont),
.key_inst_stop(key_inst_stop),
.key_mem_stop (key_mem_stop),
.key_exec(key_exec),
.key_ioreset(key_ioreset),
.key_dep(key_dep),
.key_dep_nxt(key_dep_nxt),
.key_ex(key_ex),
.key_ex_nxt(key_ex_nxt),
.sw_addr_stop(sw_addr_stop),
.sw_mem_disable(sw_mem_disable),
.sw_repeat(sw_repeat),
.sw_power(sw_power),
.sw_rim_maint(sw_rim_maint),
.mas(mas),
.datasw(datasw),
.mi(mi),
.membus_mc_wr_rs(mc_wr_rs_p0),
.membus_mc_rq_cyc(mc_rq_cyc_p0),
.membus_mc_rd_rq(mc_rd_rq_p0),
.membus_mc_wr_rq(mc_wr_rq_p0),
.membus_ma(ma_p0),
.membus_sel(sel_p0),
.membus_fmc_select(fmc_select_p0),
.membus_mb_out(mb_out_p0_p),
.membus_mai_cmc_addr_ack(cmc_addr_ack_p0),
.membus_mai_cmc_rd_rs(cmc_rd_rs_p0),
.membus_mb_in(mb_in_p0)
);
assign cmc_addr_ack_p0 = cmc_addr_ack_p0_0 | cmc_addr_ack_p0_1;
assign cmc_rd_rs_p0 = cmc_rd_rs_p0_0 | cmc_rd_rs_p0_1;
assign mb_in_p0 = mb_out_p0_p | mb_out_p0_0 | mb_out_p0_1;
fastmem fmem0(
.clk(clk),
.mc_wr_rs_p0(mc_wr_rs_p0),
.mc_rq_cyc_p0(mc_rq_cyc_p0),
.mc_rd_rq_p0(mc_rd_rq_p0),
.mc_wr_rq_p0(mc_wr_rq_p0),
.ma_p0(ma_p0),
.sel_p0(sel_p0),
.fmc_select_p0(fmc_select_p0),
.mb_in_p0(mb_in_p0),
.cmc_addr_ack_p0(cmc_addr_ack_p0_0),
.cmc_rd_rs_p0(cmc_rd_rs_p0_0),
.mb_out_p0(mb_out_p0_0),
.mc_rq_cyc_p1(1'b1),
.sel_p1(4'b0000),
.fmc_select_p1(1'b1),
.mc_rq_cyc_p2(1'b1),
.sel_p2(4'b0000),
.fmc_select_p2(1'b1),
.mc_rq_cyc_p3(1'b1),
.sel_p3(4'b0000),
.fmc_select_p3(1'b1)
);
coremem16k mem0(
.clk(clk),
.mc_wr_rs_p0(mc_wr_rs_p0),
.mc_rq_cyc_p0(mc_rq_cyc_p0),
.mc_rd_rq_p0(mc_rd_rq_p0),
.mc_wr_rq_p0(mc_wr_rq_p0),
.ma_p0(ma_p0),
.sel_p0(sel_p0),
.fmc_select_p0(fmc_select_p0),
.mb_in_p0(mb_in_p0),
.cmc_addr_ack_p0(cmc_addr_ack_p0_1),
.cmc_rd_rs_p0(cmc_rd_rs_p0_1),
.mb_out_p0(mb_out_p0_1),
.mc_rq_cyc_p1(1'b0),
.sel_p1(4'b0000),
.fmc_select_p1(1'b0),
.mc_rq_cyc_p2(1'b0),
.sel_p2(4'b0000),
.fmc_select_p2(1'b0),
.mc_rq_cyc_p3(1'b0),
.sel_p3(4'b0000),
.fmc_select_p3(1'b0)
);
initial
// #110000 $finish;
#10000 $finish;
initial begin
// #1000 apr.rlr = 8'o201;
// apr.ex_user = 1;
#100 `TESTKEY = 1;
#1000 `TESTKEY = 0;
// #3000 pdp6.key_dep = 1;
// #1000 pdp6.key_dep = 0;
end
integer i;
/* initial begin
#100;
pdp6.mem0_sw_single_step = 1;
#6000;
pdp6.mem0_sw_restart = 1;
end*/
initial begin
mem0.memsel_p0 = 0;
mem0.memsel_p1 = 0;
mem0.memsel_p2 = 0;
mem0.memsel_p3 = 0;
fmem0.memsel_p0 = 0;
fmem0.memsel_p1 = 0;
fmem0.memsel_p2 = 0;
fmem0.memsel_p3 = 0;
fmem0.fmc_p0_sel = 1;
fmem0.fmc_p1_sel = 0;
fmem0.fmc_p2_sel = 0;
fmem0.fmc_p3_sel = 0;
for(i = 0; i < 040000; i = i+1)
mem0.core[i] = 0;
mem0.core[4] = 36'o222333111666;
mem0.core['o20] = 36'o123234345456;
for(i = 0; i < 16; i = i + 1)
fmem0.ff[i] = i+1 | 36'o50000;
key_start <= 0;
key_read_in <= 0;
key_inst_cont <= 0;
key_mem_cont <= 0;
key_inst_stop <= 0;
key_mem_stop <= 0;
key_exec <= 0;
key_ioreset <= 0;
key_dep <= 0;
key_dep_nxt <= 0;
key_ex <= 0;
key_ex_nxt <= 0;
sw_addr_stop <= 0;
sw_mem_disable <= 0;
sw_repeat <= 0;
sw_power <= 0;
sw_rim_maint <= 0;
// mas <= 18'o777777;
// mas <= 18'o000000;
mas <= 18'o000004;
// mas <= 18'o000020;
// mas <= 18'o000104;
// mas <= 18'o300004;
datasw <= 36'o123456654321;
$dumpfile("dump.vcd");
$dumpvars();
reset = 0;
pdp6.key_start = 0;
pdp6.key_read_in = 0;
pdp6.key_mem_cont = 0;
pdp6.key_inst_cont = 0;
pdp6.key_mem_stop = 0;
pdp6.key_inst_stop = 0;
pdp6.key_exec = 0;
pdp6.key_io_reset = 0;
pdp6.key_dep = 0;
pdp6.key_dep_nxt = 0;
pdp6.key_ex = 0;
pdp6.key_ex_nxt = 0;
pdp6.sw_power = 0;
pdp6.sw_addr_stop = 0;
pdp6.sw_mem_disable = 0;
pdp6.sw_repeat = 0;
pdp6.sw_power = 0;
pdp6.datasw = 0;
pdp6.mas = 0;
pdp6.sw_rim_maint = 0;
pdp6.sw_repeat_bypass = 0;
pdp6.sw_art3_maint = 0;
pdp6.sw_sct_maint = 0;
pdp6.sw_split_cyc = 0;
pdp6.mem0_sw_single_step = 0;
pdp6.mem0_sw_restart = 0;
pdp6.fmem0.memsel_p0 = 0;
pdp6.fmem0.memsel_p1 = 0;
pdp6.fmem0.memsel_p2 = 0;
pdp6.fmem0.memsel_p3 = 0;
pdp6.fmem0.fmc_p0_sel = 1;
pdp6.fmem0.fmc_p1_sel = 0;
pdp6.fmem0.fmc_p2_sel = 0;
pdp6.fmem0.fmc_p3_sel = 0;
pdp6.mem0.memsel_p0 = 0;
pdp6.mem0.memsel_p1 = 0;
pdp6.mem0.memsel_p2 = 0;
pdp6.mem0.memsel_p3 = 0;
end
initial begin
#10 sw_power = 1;
#80 pdp6.apr0.pr = 8'o003;
pdp6.apr0.rlr = 8'o002;
//pdp6.apr0.ex_user = 1;
end
initial begin
#400 `TESTKEY = 1;
#1000 `TESTKEY = 0;
#1 reset = 1;
#20 reset = 0;
pdp6.datasw = 36'o111777222666;
// pdp6.mas = 18'o010100;
// pdp6.mas = 18'o000004;
pdp6.mas = 18'o000020;
//pdp6.mas = 18'o777777;
pdp6.fmem0.ff['o0] = 36'o000000010000;
pdp6.fmem0.ff['o4] = 36'o000000010004;
pdp6.mem0.core['o4] = 36'o222333111666;
pdp6.mem0.core['o20] = 36'o777000777000;
end
initial begin
#25 pdp6.sw_power = 1;
#25 pdp6.sw_power = 0;
end
// initial begin
// #7000;
// #400 key_dep = 1;
// #1000 key_dep = 0;
// end
endmodule