implemented floating point

README.md

@@ -1,17 +1,22 @@
-# PDP-6 Simulator
+# PDP-6 Emulator and Verilog Simulation
+
+This project aims to revive the PDP-6 (and later PDP-10)
+computers by DEC.
+
+I started by writing a very low level emulator in C based on
+the schematics. Later I also wrote an accurate verilog simulation
+that also works on an FPGA.
+
+Both are driven by a virtual front panel but the plan is to create
+a replica of the original panel.
 
-This project is an attempt to simulate the PDP-6 computer
-with front panel and blinkenlights on the logic level.
 The maintenance manual has flow charts, schematics and explanations:
 [Volume1](http://bitsavers.trailing-edge.com/pdf/dec/pdp6/F-67_166instrManVol1_Sep65.pdf)
 [Volume2](http://bitsavers.trailing-edge.com/pdf/dec/pdp6/F-67_166instrManVol2_Sep65.pdf)
 
 ![Screenshot of the front panel](https://raw.githubusercontent.com/aap/pdp6/master/art/screenshot.png)
 
-More recently I've been working on a verilog simulation that I want
-to put on an FPGA eventually.
-
-## Code
+## C Emulator
 
 The code is more or less a transcription of the schematics into C.
 This means you will not understand it unless you're familiar with the maintenance manual.
@@ -24,23 +29,41 @@ The timing was not accurately modeled and there is room for improvement.
 Due to the inexact timing the hardware connections (through the memory and IO bus)
 were not implemented too accurately. This may change in the future.
 
-## Building
+### Building
 
 The supplied makefile assumes gcc (there are flags to silence some stupid warnings).
 Otherwise you need SDL and pthread.
 
-## Running
+### Running
 
 The cpu (apr), console tty and paper tape/punch are implemented.
 There are no other external devices yet.
 The only things missing from the cpu is the repeat key mechanism.
 
+## Verilog Simulation
+
+The verilog code is a very accurate transcription of the schematics as well.
+Since the real machine is asynchronous I had to pull some tricks to make it
+work on an FPGA.
+The real machine uses delays that are triggered by pulses and output another
+pulse after some time. Instead of pulses I use clock enables, and delays are
+implemented by a counter synchronized to the 100MHz system clock.
+
+### FPGA
+
+My FPGA board is a Terasic Cyclone V GX Starter Kit.
+Communication with the virtual front panel is done over I²C via
+GPIO pins 2 (SCL) and 3 (SDA).
+The board's SRAM can also be read and written over I²C.
+The TTY is connected to UART over GPIO pins 4 (RX) and 5 (TX)
+
 ## File tree
 
 * `emu` source for the emulator
 * `verilog` source for the verilog simulation
 * `art` everything graphical
 * `code` some test code for the PDP-6
+* `panel6` virtual panel for the FPGA
 * `tools` tools like an assembler and linker
 * `misc` some misc. and old stuff
 

tools/as6.c

@@ -6,7 +6,7 @@
 #include <stdarg.h>
 #include "pdp6common.h"
 #include "pdp6bin.h"
-#include "../src/args.h"
+#include "args.h"
 
 #define nil NULL
 
@@ -431,28 +431,58 @@ Token
 symnum(char *s)
 {
 	Token t;
-	int isnum;
+	int neg, exp;
 	word n;
+	double f, e;
 	char *symp;
 
-	isnum = 1;
-	symp = s;
 	n = 0;
-	while(*s){
-		if(!isdigit(*s))
-			isnum = 0;
-		else if(isnum){
-			symp++;	/* ignore leading digits for symbols */
-			n = n*radix + *s-'0';
-		}
+	f = 0.0;
+	while(isdigit(*s)){
+		n = n*radix + *s-'0';
+		f = f*10.0 + *s-'0';
 		s++;
 	}
-	if(isnum){
-		t.type = Word;
-		t.w = n;
-	}else{
+	symp = s;
+	if(*s == '.'){
+		s++;
+		e = 1.0/10.0;
+		while(isdigit(*s)){
+			f += (*s-'0')*e;
+			e /= 10.0;
+			s++;
+		}
+/* NOTE: doesn't work since token() chops off + and -
+		if(*s == 'e' || *s == 'E'){
+			s++;
+			neg = 0;
+			if(*s == '+')
+				s++;
+			else if(*s == '-'){
+				neg = 1;
+				s++;
+			}
+			exp = 0;
+			while(isdigit(*s)){
+				exp = exp*10 + *s-'0';
+				s++;
+			}
+			while(exp--)
+				if(neg)
+					f /= 10.0;
+				else
+					f *= 10.0;
+		}
+*/
+		n = dtopdp(f);
+	}
+
+	if(*s){
 		t.type = Symbol;
 		t.s = getsym(sixbit(symp));
+	}else {
+		t.type = Word;
+		t.w = n;
 	}
 	return t;
 }

tools/ld6.c

@@ -5,7 +5,7 @@
 #include <assert.h>
 #include "pdp6common.h"
 #include "pdp6bin.h"
-#include "../args.h"
+#include "args.h"
 
 #define nil NULL
 

tools/pdp6common.c

@@ -37,6 +37,63 @@ readw(FILE *fp)
 	return w;
 }
 
+/* convert double to PDP-6 float */
+word
+dtopdp(double d)
+{
+	uint64_t x, e, m;
+	int sign;
+	word f;
+	sign = 0;
+	if(d < 0.0){
+		sign = 1;
+		d *= -1.0;
+	}
+	x = *(uint64_t*)&d;
+	/* sign is guaranteed to be 0 now */
+	e = (x >> 52) & 0x7FF;
+	m = x & 0xFFFFFFFFFFFFF;
+	e += 128-1023;
+	m >>= 25;
+	/* normalize */
+	if(x != 0){
+		m >>= 1;
+		m |= 0400000000;
+		e += 1;
+	}
+	f = e << 27;
+	f |= m;
+	if(sign)
+		f = -f & 0777777777777;
+	return f;
+}
+
+/* convert PDP-6 float to double */
+double
+pdptod(word f)
+{
+	uint64_t x, s, e, m;
+	s = 0;
+	if(f & 0400000000000){
+		f = -f & 0777777777777;
+		s = 1;
+	}
+	e = (f >> 27) & 0377;
+	m = f & 0777777777;
+	e += 1023-128;
+	/* normalize */
+	if(m != 0){
+		m &= ~0400000000;
+		m <<= 1;
+		e -= 1;
+	}
+	m <<= 25;
+	x = m;
+	x |= (e & 0x7FF) << 52;
+	x |= s << 63;
+	return *(double*)&x;
+}
+
 /* map ascii to radix50/squoze, also map lower to upper case */
 char
 ascii2rad(char c)

tools/pdp6common.h

@@ -10,6 +10,9 @@ int isneg(word w);
 void writew(word w, FILE *fp);
 word readw(FILE *fp);
 
+word dtopdp(double d);
+double pdptod(word f);
+
 char ascii2rad(char c);
 char rad2ascii(char c);
 int israd50(char c);

verilog/Makefile

@@ -1,4 +1,4 @@
-test: test.v pdp6.v apr.v core161c.v fast162.v modules.v test1.inc test2.inc
+test: test.v pdp6.v apr.v core161c.v fast162.v modules.v test1.inc test2.inc test_fp.inc
 	iverilog -o test test.v pdp6.v apr.v core161c.v fast162.v modules.v
 
 test_dec: test_dec.v pdp6.v apr.v core161c.v fast162.v modules.v

verilog/apr.v

@@ -112,6 +112,7 @@ module apr(
 	/*
 	 * KEY
 	 */
+	// TODO: repeat
 	// reg run;
 	reg key_ex_st;
 	reg key_dep_st;
@@ -1015,7 +1016,6 @@ module apr(
 			mb[0:17] <= mb[0:17] | pc;
 		if(mb_fm_ir1)
 			mb[18:35] <= mb[18:35] | ir;
-		// TODO: other single bits?
 		if(mb1_8_clr)
 			mb[1:8] <= 0;
 		if(mb1_8_set)
@@ -1656,9 +1656,19 @@ module apr(
 	 */
 	reg fsf1;
 	wire fsc = ir_fsc;
-	wire fst0 = 0;
-	wire fst0a = 0;
-	wire fst1 = 0;
+	wire fst0;
+	wire fst0a;
+	wire fst1;
+
+	pa fs_pa0(.clk(clk), .reset(reset),
+		.in(et3 & fsc),
+		.p(fst0));
+	pa fs_pa1(.clk(clk), .reset(reset),
+		.in(et3 & fsc & ar[0]),
+		.p(fst1));
+	pa fs_pa2(.clk(clk), .reset(reset),
+		.in(sat3 & fsf1),
+		.p(fst0a));
 
 	always @(posedge clk) begin
 		if(ds_clr | fst0a)
@@ -1954,31 +1964,119 @@ module apr(
 	reg faf3;
 	reg faf4;
 
-	wire fat0 = 0;
-	wire fat1 = 0;
-	wire fat1a = 0;
-	wire fat1b = 0;
-	wire fat2 = 0;
-	wire fat3 = 0;
-	wire fat4 = 0;
-	wire fat5 = 0;
-	wire fat5a = 0;
-	wire fat6 = 0;
-	wire fat7 = 0;
-	wire fat8 = 0;
-	wire fat8a = 0;
-	wire fat9 = 0;
-	wire fat10 = 0;
+	wire fat0;
+	wire fat1;
+	wire fat1a;
+	wire fat1b;
+	wire fat2;
+	wire fat3;
+	wire fat4;
+	wire fat5;
+	wire fat5a;
+	wire fat6;
+	wire fat7;
+	wire fat8;
+	wire fat8a;
+	wire fat9;
+	wire fat10;
+
+	pa fa_pa0(.clk(clk), .reset(reset),
+		.in(et0 & ir_fad |
+		    et4 & ir_fsb),
+		.p(fat0));
+	pa fa_pa1(.clk(clk), .reset(reset),
+		.in(fat0_D),
+		.p(fat1));
+	pa fa_pa2(.clk(clk), .reset(reset),
+		.in(sat3 & faf2),
+		.p(fat1a));
+	pa fa_pa3(.clk(clk), .reset(reset),
+		.in(fat1_D),
+		.p(fat1b));
+	pa fa_pa4(.clk(clk), .reset(reset),
+		.in(fat1a & ~sc[0]),
+		.p(fat2));
+	pa fa_pa5(.clk(clk), .reset(reset),
+		.in(fat2_D),
+		.p(fat3));
+	pa fa_pa6(.clk(clk), .reset(reset),
+		.in(fat1a & sc[0]),
+		.p(fat4));
+	pa fa_pa7(.clk(clk), .reset(reset),
+		.in((fat3_D | fat4_D) & sc0_2_eq_7),
+		.p(fat5));
+	pa fa_pa8(.clk(clk), .reset(reset),
+		.in(sct2 & faf3),
+		.p(fat5a));
+	pa fa_pa9(.clk(clk), .reset(reset),
+		.in((fat3_D | fat4_D) & ~sc0_2_eq_7),
+		.p(fat6));
+	pa fa_pa10(.clk(clk), .reset(reset),
+		.in(fat5a_D),
+		.p(fat7));
+	pa fa_pa11(.clk(clk), .reset(reset),
+		.in(fat7_D),
+		.p(fat8));
+	pa fa_pa12(.clk(clk), .reset(reset),
+		.in(fat8_D),
+		.p(fat8a));
+	pa fa_pa13(.clk(clk), .reset(reset),
+		.in(fat8a_D),
+		.p(fat9));
+	pa fa_pa14(.clk(clk), .reset(reset),
+		.in(ar_t3 & faf4),
+		.p(fat10));
+
+	wire fat0_D, fat1_D, fat2_D, fat3_D, fat4_D;
+	wire fat5a_D, fat7_D, fat8_D, fat8a_D;
+	dly100ns fa_dly0(.clk(clk), .reset(reset),
+		.in(fat0),
+		.p(fat0_D));
+	dly50ns fa_dly1(.clk(clk), .reset(reset),
+		.in(fat1),
+		.p(fat1_D));
+	dly150ns fa_dly2(.clk(clk), .reset(reset),
+		.in(fat2),
+		.p(fat2_D));
+	dly150ns fa_dly3(.clk(clk), .reset(reset),
+		.in(fat3),
+		.p(fat3_D));
+	dly100ns fa_dly4(.clk(clk), .reset(reset),
+		.in(fat4),
+		.p(fat4_D));
+	dly100ns fa_dly5(.clk(clk), .reset(reset),
+		.in(fat5a),
+		.p(fat5a_D));
+	dly100ns fa_dly6(.clk(clk), .reset(reset),
+		.in(fat7),
+		.p(fat7_D));
+	dly50ns fa_dly7(.clk(clk), .reset(reset),
+		.in(fat8),
+		.p(fat8_D));
+	dly100ns fa_dly8(.clk(clk), .reset(reset),
+		.in(fat8a),
+		.p(fat8a_D));
 
 	always @(posedge clk) begin
 		if(mp_clr | fat1b | fat10)
 			faf1 <= 0;
+		if(fat0 | fat5a)
+			faf1 <= 1;
+
 		if(mp_clr | fat1a)
 			faf2 <= 0;
+		if(fat1b)
+			faf2 <= 1;
+
 		if(mp_clr | fat5a)
 			faf3 <= 0;
+		if(fat5)
+			faf3 <= 1;
+
 		if(mp_clr | fat10)
 			faf4 <= 0;
+		if(fat9)
+			faf4 <= 1;
 	end
 
 	/*
@@ -1987,15 +2085,35 @@ module apr(
 	reg fmf1;
 	reg fmf2;
 
-	wire fmt0 = 0;
-	wire fmt0a = 0;
-	wire fmt0b = 0;
+	wire fmt0;
+	wire fmt0a;
+	wire fmt0b;
+
+	pa fm_pa0(.clk(clk), .reset(reset),
+		.in(et0 & ir_fmp),
+		.p(fmt0));
+	pa fm_pa1(.clk(clk), .reset(reset),
+		.in(fpt4 & fmf1),
+		.p(fmt0a));
+	pa fm_pa2(.clk(clk), .reset(reset),
+		.in(mst6 & fmf2),
+		.p(fmt0b));
+
+	wire fmt0b_D;
+	dly100ns fm_dly0(.clk(clk), .reset(reset),
+		.in(fmt0b),
+		.p(fmt0b_D));
 
 	always @(posedge clk) begin
 		if(mp_clr | fmt0a)
 			fmf1 <= 0;
+		if(fmt0)
+			fmf1 <= 1;
+
 		if(mp_clr | fmt0b)
 			fmf2 <= 0;
+		if(fmt0a)
+			fmf2 <= 1;
 	end
 
 	/*
@@ -2004,16 +2122,39 @@ module apr(
 	reg fdf1;
 	reg fdf2;
 
-	wire fdt0 = 0;
-	wire fdt0a = 0;
-	wire fdt0b = 0;
-	wire fdt1 = 0;
+	wire fdt0;
+	wire fdt0a;
+	wire fdt0b;
+	wire fdt1;
+
+	pa fd_pa0(.clk(clk), .reset(reset),
+		.in(et0 & ir_fdv),
+		.p(fdt0));
+	pa fd_pa1(.clk(clk), .reset(reset),
+		.in(fpt4 & fdf1),
+		.p(fdt0a));
+	pa fd_pa2(.clk(clk), .reset(reset),
+		.in(dst21a & fdf2),
+		.p(fdt0b));
+	pa fd_pa3(.clk(clk), .reset(reset),
+		.in(fdt0b_D),
+		.p(fdt1));
+
+	wire fdt0b_D;
+	dly100ns fd_dly0(.clk(clk), .reset(reset),
+		.in(fdt0b),
+		.p(fdt0b_D));
 
 	always @(posedge clk) begin
 		if(mp_clr | fdt0a)
 			fdf1 <= 0;
+		if(fdt0)
+			fdf1 <= 1;
+
 		if(mp_clr | fdt0b)
 			fdf2 <= 0;
+		if(fdt0a)
+			fdf2 <= 1;
 	end
 
 	/*
@@ -2021,25 +2162,72 @@ module apr(
 	 */
 	reg fpf1;
 	reg fpf2;
-	wire fp_ar0_xor_fmf1 = 0;
-	wire fp_ar0_xor_mb0_xor_fmf1 = 0;
-	wire fp_mb0_eq_fmf1 = 0;
+	wire fp_ar0_xor_fmf1 = ar[0] ^ fmf1;
+	wire fp_ar0_xor_mb0_xor_fmf1 = fp_ar0_xor_fmf1 ^ mb[0];
+	wire fp_mb0_eq_fmf1 = mb[0] == fmf1;
 
-	wire fpt0 = 0;
-	wire fpt01 = 0;
-	wire fpt1 = 0;
-	wire fpt1a = 0;
-	wire fpt1aa = 0;
-	wire fpt1b = 0;
-	wire fpt2 = 0;
-	wire fpt3 = 0;
-	wire fpt4 = 0;
+	wire fpt0;
+	wire fpt01;
+	wire fpt1;
+	wire fpt1a;
+	wire fpt1aa;
+	wire fpt1b;
+	wire fpt2;
+	wire fpt3;
+	wire fpt4;
+
+	pa fp_pa0(.clk(clk), .reset(reset),
+		.in(fmt0 | fdt0),
+		.p(fpt0));
+	pa fp_pa1(.clk(clk), .reset(reset),
+		.in(fpt0),
+		.p(fpt01));
+	pa fp_pa2(.clk(clk), .reset(reset),
+		.in(fpt01_D),
+		.p(fpt1));
+	pa fp_pa3(.clk(clk), .reset(reset),
+		.in(sat3 & fpf1),
+		.p(fpt1a));
+	pa fp_pa4(.clk(clk), .reset(reset),
+		.in(fpt1a_D),
+		.p(fpt1aa));
+	pa fp_pa5(.clk(clk), .reset(reset),
+		.in(sat3 & fpf2),
+		.p(fpt1b));
+	pa fp_pa6(.clk(clk), .reset(reset),
+		.in(fpt1a & fp_ar0_xor_mb0_xor_fmf1),
+		.p(fpt2));
+	pa fp_pa7(.clk(clk), .reset(reset),
+		.in(fpt1b_D),
+		.p(fpt3));
+	pa fp_pa8(.clk(clk), .reset(reset),
+		.in(fpt3_D),
+		.p(fpt4));
+
+	wire fpt01_D, fpt1a_D, fpt1b_D, fpt3_D;
+	dly100ns fp_dly0(.clk(clk), .reset(reset),
+		.in(fpt01),
+		.p(fpt01_D));
+	dly100ns fp_dly1(.clk(clk), .reset(reset),
+		.in(fpt1a),
+		.p(fpt1a_D));
+	dly100ns fp_dly2(.clk(clk), .reset(reset),
+		.in(fpt1b),
+		.p(fpt1b_D));
+	dly100ns fp_dly3(.clk(clk), .reset(reset),
+		.in(fpt3),
+		.p(fpt3_D));
 
 	always @(posedge clk) begin
 		if(mp_clr | fpt1a)
 			fpf1 <= 0;
+		if(fpt1)
+			fpf1 <= 1;
+
 		if(mp_clr | fpt1b)
 			fpf2 <= 0;
+		if(fpt1aa)
+			fpf2 <= 1;
 	end
 
 	/*
@@ -2367,34 +2555,90 @@ module apr(
 	reg nrf1;
 	reg nrf2;
 	reg nrf3;
-	wire nr_ar9_eq_ar0 = 0;
+	wire nr_ar9_eq_ar0 = ar[9] == ar[0];
 	wire nr_round = ~nrf3 & mq[1] & ir[6];
-	wire nr_ar_eq_0_AND_mq1_0;
+	wire nr_ar_eq_0_AND_mq1_0 = ar == 0 & ~mq[1];
 
-	wire nrt05 = 0;
-	wire nrt0 = 0;
-	wire nrt01 = 0;
-	wire nrt1 = 0;
-	wire nrt2 = 0;
-	wire nrt3 = 0;
-	wire nrt31 = 0;
-	wire nrt4 = 0;
-	wire nrt5 = 0;
-	wire nrt5a = 0;
+	wire nrt05;
+	wire nrt0;
+	wire nrt01;
+	wire nrt1;
+	wire nrt2;
+	wire nrt3;
+	wire nrt31;
+	wire nrt4;
+	wire nrt5;
+	wire nrt5a;
 	wire nrt6;
 
 	pa nr_pa0(.clk(clk), .reset(reset),
-		.in(mpt0a & ir[6] |
-		    mpt2_D),	// TODO
+		.in(fdt1 | fat10 | nrt5a),
+		.p(nrt05));
+	pa nr_pa1(.clk(clk), .reset(reset),
+		.in(nrt05_D),
+		.p(nrt0));
+	pa nr_pa2(.clk(clk), .reset(reset),
+		.in(nrt0),
+		.p(nrt01));
+	pa nr_pa3(.clk(clk), .reset(reset),
+		.in((fmt0b_D | nrt01_D) & ~nr_ar_eq_0_AND_mq1_0),
+		.p(nrt1));
+	pa nr_pa4(.clk(clk), .reset(reset),
+		.in((nrt1_D | nrt2_D) & nr_ar9_eq_ar0 & ~ar_eq_fp_half),
+		.p(nrt2));
+	pa nr_pa5(.clk(clk), .reset(reset),
+		.in((nrt1_D | nrt2_D) & (~nr_ar9_eq_ar0 | ar_eq_fp_half)),
+		.p(nrt3));
+	pa nr_pa6(.clk(clk), .reset(reset),
+		.in(nrt3),
+		.p(nrt31));
+	pa nr_pa7(.clk(clk), .reset(reset),
+		.in(nrt31_D & ~nr_round),
+		.p(nrt4));
+	pa nr_pa8(.clk(clk), .reset(reset),
+		.in(nrt31_D & nr_round),
+		.p(nrt5));
+	pa nr_pa9(.clk(clk), .reset(reset),
+		.in(ar_t3 & nrf1),
+		.p(nrt5a));
+	pa nr_pa10(.clk(clk), .reset(reset),
+		.in((fmt0b_D | nrt01_D) & nr_ar_eq_0_AND_mq1_0 |
+		    nrt4 |
+		    mpt0a & ir[6] |
+		    mpt2_D),
 		.p(nrt6));
 
+	wire nrt05_D, nrt01_D, nrt1_D, nrt2_D, nrt31_D;
+	dly100ns nr_dly0(.clk(clk), .reset(reset),
+		.in(nrt05),
+		.p(nrt05_D));
+	dly200ns nr_dly1(.clk(clk), .reset(reset),
+		.in(nrt01),
+		.p(nrt01_D));
+	dly100ns nr_dly2(.clk(clk), .reset(reset),
+		.in(nrt1),
+		.p(nrt1_D));
+	dly150ns nr_dly3(.clk(clk), .reset(reset),
+		.in(nrt2),
+		.p(nrt2_D));
+	dly100ns nr_dly4(.clk(clk), .reset(reset),
+		.in(nrt31),
+		.p(nrt31_D));
+
 	always @(posedge clk) begin
 		if(mp_clr | nrt5a)
 			nrf1 <= 0;
+		if(nrt5)
+			nrf1 <= 1;
+
 		if(mp_clr) begin
 			nrf2 <= 0;
 			nrf3 <= 0;
 		end
+		if(nrt05 | fdt0b | fmt0b)
+			nrf2 <= 1;
+		if(nrt5a)
+			nrf3 <= 1;
 	end
 
 	/*
@@ -2923,7 +3167,10 @@ module apr(
 	wire cpa = iobus_ios == 0;
 	wire cpa_cono_set = cpa & iobus_cono_set;
 	wire cpa_status = cpa & iobus_iob_fm_status;
-	wire cpa_clock_flag_set = 0;
+	wire cpa_clock_flag_set;
+
+	clk60hz cpa_clk(.clk(clk),
+		.outclk(cpa_clock_flag_set));
 
 	wire cpa_req_enable = cpa_illeg_op | cpa_non_exist_mem | cpa_pdl_ov |
 		cpa_clock_enable & cpa_clock_flag |

verilog/modules.v

@@ -1,3 +1,17 @@
+// input 100mhz, output ~60hz
+module clk60hz(
+	input wire clk,
+	output wire outclk
+);
+	reg [21:0] cnt = 0;
+	assign outclk = cnt == 1666666;
+	always @(posedge clk)
+		if(outclk)
+			cnt <= 0;
+		else
+			cnt <= cnt + 22'b1;
+endmodule
+
 module pg(
 	input clk,
 	input reset,

verilog/test.gtkw

@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v3.3.76 (w)1999-2016 BSI
-[*] Sat Dec 10 18:05:06 2016
+[*] Sun Dec 11 15:59:05 2016
 [*]
 [dumpfile] "/home/aap/src/pdp6/verilog/dump.vcd"
-[dumpfile_mtime] "Sat Dec 10 17:52:00 2016"
-[dumpfile_size] 335826
+[dumpfile_mtime] "Sun Dec 11 15:55:54 2016"
+[dumpfile_size] 256855
 [savefile] "/home/aap/src/pdp6/verilog/test.gtkw"
-[timestart] 4810
+[timestart] 0
 [size] 1920 1080
 [pos] -1 -1
-*-11.555068 17575 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-11.555068 5260 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] test.
 [treeopen] test.pdp6.
 [sst_width] 337
@@ -434,7 +434,7 @@ test.pdp6.apr0.pc_set_OR_pc_inc
 test.pdp6.apr0.pc_set_enable
 @1401200
 -misc
-@c00200
+@c00201
 -cpa
 @28
 test.pdp6.apr0.cpa
@@ -448,6 +448,7 @@ test.pdp6.apr0.cpa_illeg_op
 test.pdp6.apr0.cpa_non_exist_mem
 test.pdp6.apr0.cpa_clock_enable
 test.pdp6.apr0.cpa_clock_flag
+test.pdp6.apr0.cpa_clock_flag_set
 test.pdp6.apr0.cpa_pc_chg_enable
 test.pdp6.apr0.cpa_pdl_ov
 test.pdp6.apr0.cpa_arov_enable
@@ -460,7 +461,7 @@ test.pdp6.apr0.cpa_iob[0:35]
 test.pdp6.apr0.iob_pi_req[1:7]
 test.pdp6.apr0.iobus_pi_req[1:7]
 test.pdp6.apr0.cpa_req[1:7]
-@1401200
+@1401201
 -cpa
 @c00200
 -shift
@@ -578,7 +579,7 @@ test.pdp6.apr0.mst5
 test.pdp6.apr0.mst6
 @1401200
 -MS
-@c00201
+@c00200
 -DS
 @28
 test.pdp6.apr0.ds_div_t0
@@ -628,7 +629,93 @@ test.pdp6.apr0.dsf7
 test.pdp6.apr0.dsf7_xor_mq0
 test.pdp6.apr0.dsf8
 test.pdp6.apr0.dsf9
-@1401201
+@1401200
 -DS
+@c00200
+-FM
+@28
+test.pdp6.apr0.fmt0
+test.pdp6.apr0.fmf1
+test.pdp6.apr0.fmt0a
+test.pdp6.apr0.fmf2
+test.pdp6.apr0.fmt0b
+@1401200
+-FM
+@c00200
+-FD
+@28
+test.pdp6.apr0.fdt0
+test.pdp6.apr0.fdf1
+test.pdp6.apr0.fdt0a
+test.pdp6.apr0.fdf2
+test.pdp6.apr0.fdt0b
+test.pdp6.apr0.fdt1
+@1401200
+-FD
+@c00200
+-FP
+@28
+test.pdp6.apr0.fpt0
+test.pdp6.apr0.fpt01
+test.pdp6.apr0.fpt1
+test.pdp6.apr0.fpf1
+test.pdp6.apr0.fpt1a
+test.pdp6.apr0.fpt1aa
+test.pdp6.apr0.fpf2
+test.pdp6.apr0.fpt1b
+test.pdp6.apr0.fpt2
+test.pdp6.apr0.fpt3
+test.pdp6.apr0.fpt4
+@200
+-
+@28
+test.pdp6.apr0.fp_ar0_xor_fmf1
+test.pdp6.apr0.fp_ar0_xor_mb0_xor_fmf1
+test.pdp6.apr0.fp_mb0_eq_fmf1
+@1401200
+-FP
+@c00200
+-NR
+@28
+test.pdp6.apr0.ar_eq_fp_half
+test.pdp6.apr0.nr_ar9_eq_ar0
+test.pdp6.apr0.nr_round
+test.pdp6.apr0.nrt05
+test.pdp6.apr0.nrt0
+test.pdp6.apr0.nrt01
+test.pdp6.apr0.nrt1
+test.pdp6.apr0.nrt2
+test.pdp6.apr0.nrt3
+test.pdp6.apr0.nrt31
+test.pdp6.apr0.nrt4
+test.pdp6.apr0.nrt5
+test.pdp6.apr0.nrt5a
+test.pdp6.apr0.nrt6
+@1401200
+-NR
+@c00200
+-FA
+@28
+test.pdp6.apr0.fat0
+test.pdp6.apr0.fat1
+test.pdp6.apr0.faf1
+test.pdp6.apr0.fat1b
+test.pdp6.apr0.faf2
+test.pdp6.apr0.fat1a
+test.pdp6.apr0.fat2
+test.pdp6.apr0.fat3
+test.pdp6.apr0.fat4
+test.pdp6.apr0.fat5
+test.pdp6.apr0.faf3
+test.pdp6.apr0.fat5a
+test.pdp6.apr0.fat6
+test.pdp6.apr0.fat7
+test.pdp6.apr0.fat8
+test.pdp6.apr0.fat8a
+test.pdp6.apr0.fat9
+test.pdp6.apr0.faf4
+test.pdp6.apr0.fat10
+@1401200
+-FA
 [pattern_trace] 1
 [pattern_trace] 0

verilog/test.v

@@ -157,7 +157,8 @@ module test;
 			pdp6.fmem0.ff[i] = 0;
 
 		//`include "test1.inc"
-		`include "test2.inc"
+		//`include "test2.inc"
+		`include "test_fp.inc"
 	end
 
 	wire [0:35] mem0scope = pdp6.mem0.core['o1000];

verilog/test_fp.inc

@@ -0,0 +1,16 @@
+pdp6.fmem0.ff['o0] = 36'o201_400000000;	// 1.0
+pdp6.fmem0.ff['o1] = 36'o202_400000000;	// 2.0
+pdp6.fmem0.ff['o2] = 36'o200_754213603;
+pdp6.fmem0.ff['o3] = 36'o202_561251001;
+
+pdp6.mem0.core['o100] = 36'o132_000_000004;	// FSC 0,4
+pdp6.mem0.core['o101] = 36'o132_000_777776;	// FSC 0,-2
+
+pdp6.mem0.core['o110] = 36'o160_100_000003;	// FMP 2,3
+
+pdp6.mem0.core['o120] = 36'o170_100_000003;	// FDV 2,3
+
+pdp6.mem0.core['o130] = 36'o140_100_000003;	// FAD 2,3
+pdp6.mem0.core['o131] = 36'o150_100_000003;	// FSB 2,3
+
+pdp6.mas = 18'o000131;