mirror of
https://github.com/aap/pdp6.git
synced 2026-04-10 23:01:26 +00:00
work on IOT, AR, SH and SC
This commit is contained in:
aap
@@ -29,7 +29,7 @@
|
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inkscape:pageopacity="0.0"
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||||
inkscape:pageshadow="2"
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||||
inkscape:zoom="2.2066156"
|
||||
inkscape:cx="406.39064"
|
||||
inkscape:cx="314.62114"
|
||||
inkscape:cy="326.91335"
|
||||
inkscape:document-units="mm"
|
||||
inkscape:current-layer="layer7"
|
||||
@@ -37,8 +37,8 @@
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||||
units="mm"
|
||||
inkscape:window-width="1920"
|
||||
inkscape:window-height="1080"
|
||||
inkscape:window-x="0"
|
||||
inkscape:window-y="0"
|
||||
inkscape:window-x="32"
|
||||
inkscape:window-y="18"
|
||||
inkscape:window-maximized="0"
|
||||
inkscape:snap-global="true"
|
||||
showguides="false"
|
||||
@@ -231,7 +231,7 @@
|
||||
cy="92.126007"
|
||||
cx="139.42914"
|
||||
id="circle4665"
|
||||
style="fill:#ffd700;fill-opacity:1;stroke:#000000;stroke-width:1.35701132;stroke-linecap:butt;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" />
|
||||
style="fill:#ffbf00;fill-opacity:1;stroke:#000000;stroke-width:1.35701132;stroke-linecap:butt;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" />
|
||||
<circle
|
||||
inkscape:export-ydpi="35.524475"
|
||||
inkscape:export-xdpi="35.524475"
|
||||
|
||||
|
Before Width: | Height: | Size: 12 KiB After Width: | Height: | Size: 12 KiB |
BIN
art/lamp_on.png
BIN
art/lamp_on.png
Binary file not shown.
|
Before Width: | Height: | Size: 512 B After Width: | Height: | Size: 510 B |
443
verilog/apr.v
443
verilog/apr.v
@@ -129,8 +129,7 @@ module apr(
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wire key_ma_fm_masw1 = kt2 & key_ma_fm_mas;
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wire key_ma_inc = kt1 & key_ex_OR_dep_nxt;
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wire key_ar_clr = kt1 & key_execute_OR_dp_OR_dp_nxt;
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wire key_ar_fm_datasw1 = kt2 & key_execute_OR_dp_OR_dp_nxt |
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cpa & iobus_iob_fm_datai;
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wire key_ar_fm_datasw1;
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wire key_rd = kt3 & key_ex_OR_ex_nxt;
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wire key_wr = kt3 & key_dp_OR_dp_nxt;
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@@ -138,16 +137,18 @@ module apr(
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pg key_pg0(.clk(clk), .reset(reset), .in(key_inst_stop), .p(run_clr));
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pg key_pg1(.clk(clk), .reset(reset), .in(sw_power), .p(mr_pwr_clr));
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pg key_pg2(.clk(clk), .reset(reset), .in(key_manual), .p(kt0));
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pg key_pg3(.clk(clk), .reset(reset),
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.in(kt2 & key_execute_OR_dp_OR_dp_nxt |
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cpa & iobus_iob_fm_datai),
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.p(key_ar_fm_datasw1));
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pa key_pa0(.clk(clk), .reset(reset), .in(kt0), .p(kt0a));
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dly100ns key_dly0(.clk(clk), .reset(reset), .in(kt0a), .p(kt0a_D));
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pa key_pa1(.clk(clk), .reset(reset),
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.in(kt0a_D & ~run |
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kt0a & key_mem_cont | // TODO: check run?
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st7 & run & key_ex_OR_dep_st),
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.p(kt1));
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dly200ns key_dly1(.clk(clk), .reset(reset), .in(kt1), .p(kt1_D));
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pa key_pa2(.clk(clk), .reset(reset), .in(kt1_D), .p(kt2));
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dly200ns key_dly2(.clk(clk), .reset(reset), .in(kt2), .p(kt2_D));
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pa key_pa3(.clk(clk), .reset(reset), .in(kt2_D), .p(kt3));
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pa key_pa4(.clk(clk), .reset(reset),
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.in(kt3 & key_execute |
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@@ -163,6 +164,10 @@ module apr(
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.in(key_rdwr & mc_rs_t1),
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.p(key_rdwr_ret));
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dly100ns key_dly0(.clk(clk), .reset(reset), .in(kt0a), .p(kt0a_D));
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dly200ns key_dly1(.clk(clk), .reset(reset), .in(kt1), .p(kt1_D));
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dly200ns key_dly2(.clk(clk), .reset(reset), .in(kt2), .p(kt2_D));
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/* add to this as needed */
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always @(posedge reset) begin
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run <= 0;
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@@ -445,7 +450,7 @@ module apr(
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ar_t3 & et4_ar_pse),
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.p(et4));
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pa e_pa5(.clk(clk), .reset(reset),
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.in(et4_D & ~et5_inh | iot_t3_D),
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.in(et4_D & ~et5_inh /* XXX | iot_t3_D*/),
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.p(et5));
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pa e_pa6(.clk(clk), .reset(reset),
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.in(et5_D & e_long),
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@@ -713,8 +718,8 @@ module apr(
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wire fwt_11 = ir_fwt & ir[7:8] == 3;
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/* HWT */
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wire hwt_lt_set = hwt_rt & ir[4] | (~ir[5] | mb[18]);
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wire hwt_rt_set = hwt_lt & ir[4] | (~ir[5] | mb[0]);
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wire hwt_lt_set = hwt_rt & ir[4] & (~ir[5] | mb[18]);
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wire hwt_rt_set = hwt_lt & ir[4] & (~ir[5] | mb[0]);
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wire hwt_lt = ir_hwt & ~ir[3];
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wire hwt_rt = ir_hwt & ir[3];
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wire hwt_swap = ir_hwt & ir[6];
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@@ -844,7 +849,7 @@ module apr(
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reg ex_pi_sync;
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reg ex_ill_op;
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wire ex_clr = mr_start | cpa & iobus_datao_clear;
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wire ex_set = mr_start | cpa & iobus_datao_set;
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wire ex_set = cpa & iobus_datao_set;
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wire ex_ir_uuo = ir_jrst_a & ir_9_OR_10 & ex_user |
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ir_iot_a & ~ex_pi_sync & ex_user & ~cpa_iot_user |
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ex_uuo_sync & ir_uuo_a;
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@@ -1077,30 +1082,34 @@ module apr(
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wire ar_fm_mbltJ_et4 = hwt_lt | iot_cono;
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wire ar_fm_mbrtJ_et4 = hwt_rt;
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wire ar1_8_clr = 0;
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wire ar1_8_set = 0;
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wire ar_add = 0;
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wire ar_sub = 0;
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wire ar_inc = 0;
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wire ar_incdec_lt_rt = 0;
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wire ar_dec = 0;
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wire ar_sbr = 0;
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wire ar_cry_comp;
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wire ar_fm_sc1_8J = 0;
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wire ar0_5_fm_sc3_8J = 0;
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wire ar_incdec_t0 = 0;
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wire ar_negate_t0 = 0;
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wire ar_incdec_t1 = 0;
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wire ar17_cry_in = 0;
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wire ar_as_t0 = 0;
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wire ar_incdec_t0;
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wire ar_negate_t0;
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wire ar_incdec_t1;
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// these two are a bit of a hack
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wire ar35_cry_in = ar_incdec_t1;
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wire ar17_cry_in = ar_incdec_t1 & (ar_incdec_lt_rt | ir_blt);
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wire ar_as_t0;
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wire ar_as_t1;
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wire ar_as_t2;
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wire ar_t3;
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wire ar_cry_comp;
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wire ar1_8_clr = (fpt3 | fat5) & ~ar[0];
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wire ar1_8_set = (fpt3 | fat5) & ar[0];
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wire ar_fm_sc1_8J = nrt4 | fst0a;
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wire ar0_5_fm_sc3_8J = cht6 & ch_inc_op;
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wire ar_add = as_plus;
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wire ar_sub = as_minus | accp;
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wire ar_inc = memac_inc | jp_push | jp_pushj | iot_blk |
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ir_aobjp | ir_aobjn;
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wire ar_incdec_lt_rt = iot_blk | ir_aobjp | ir_aobjn | jp_AND_ir6_0;
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wire ar_dec = memac_dec | jp_pop | jp_popj;
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wire ar_sbr = fwt_negate | ar_add | ar_sub | ar_inc | ar_dec | ir_fsb;
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wire ar_flag_clr = mr_start | et0 & ir_jrst & ir[11];
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wire ar_jrst_AND_ir11 = ir_jrst & ir[11];
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wire ar_flag_set = et1 & ar_jrst_AND_ir11;
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wire ar_jfcl_clr = et10 & ir_jfcl;
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wire ar_eq_fp_half = ar == 36'o000400000000;
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wire ar_eq_0 = ar == 0;
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wire ar0_xor_ar1 = ar[0] ^ ar[1];
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@@ -1112,11 +1121,26 @@ module apr(
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wire set_flags_et10 = et10 & (memac | ir_as);
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pa ar_pa0(); // AR+-1 T0
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pa ar_pa1(); // AR NEGATE T0
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pa ar_pa2(); // AR+-1 T1
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pa ar_pa0(.clk(clk), .reset(reset),
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.in(et3 & ar_dec),
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.p(ar_incdec_t0));
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pa ar_pa1(.clk(clk), .reset(reset),
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.in(et3 & fwt_negate |
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et3 & ir_fsb |
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cfac_ar_negate),
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.p(ar_negate_t0));
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pa ar_pa2(.clk(clk), .reset(reset),
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.in(ar_incdec_t0_D |
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ar_negate_t0_D |
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et3 & ar_inc |
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blt_t5 | nrt5 | cht4),
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.p(ar_incdec_t1));
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pa ar_pa3(); // AR17 CRY IN
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pa ar_pa4(); // AR AS T0
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pa ar_pa4(.clk(clk), .reset(reset),
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.in(et3 & ar_sub |
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cfac_ar_sub |
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blt_t3),
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.p(ar_as_t0));
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pa ar_pa5(.clk(clk), .reset(reset),
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.in(ar_as_t0_D | et3 & ar_add |
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at3 | cfac_ar_add),
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@@ -1149,13 +1173,25 @@ module apr(
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dly100ns ar_dly4(.clk(clk), .reset(reset),
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.in(ar_cry_comp),
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.p(ar_cry_comp_D));
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dly100ns ar_dly5(.clk(clk), .reset(reset),
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.in(ar_incdec_t0),
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.p(ar_incdec_t0_D));
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dly100ns ar_dly6(.clk(clk), .reset(reset),
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.in(ar_negate_t0),
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.p(ar_negate_t0_D));
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wire mst1_D;
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dly50ns ar_dly5(.clk(clk), .reset(reset),
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dly50ns ar_dly7(.clk(clk), .reset(reset),
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.in(mst1),
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.p(mst1_D));
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wire [0:35] ar_mb_cry = mb & ~ar;
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wire [0:35] ar_cry_in = ar_cry_initiate ? { mb&~ar, 1'b0 } :
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ar35_cry_in & ar17_cry_in ? 36'o000001000001 :
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ar35_cry_in ? 36'o000000000001 :
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ar17_cry_in ? 36'o000001000000 :
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0;
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// hold the cry out temporarily
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reg cry0, cry1;
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@@ -1165,14 +1201,14 @@ module apr(
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ar[0:17] <= 0;
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if(arrt_clr)
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ar[18:35] <= 0;
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if(ar_cry_initiate) begin
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cry1 <= (ar[1:35] + { ar_mb_cry[2:35], 1'b0 }) + 36'o0 >> 35;
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{cry0, ar} <= ar + { ar_mb_cry[1:35], 1'b0 };
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if(ar_cry_in) begin
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cry1 <= (ar[1:35] + ar_cry_in[1:35]) + 36'o0 >> 35;
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{cry0, ar} <= ar + ar_cry_in;
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end
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if(arlt_com)
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ar[0:17] <= ~ar[0:17];
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if(arrt_com)
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ar[0:17] <= ~ar[0:17];
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ar[18:35] <= ~ar[18:35];
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if(arlt_fm_mb_xor)
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ar[0:17] <= ar[0:17] ^ mb[0:17];
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if(arrt_fm_mb_xor)
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@@ -1199,9 +1235,19 @@ module apr(
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ar[0:17] <= ar[0:17] | iob[0:17];
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if(arrt_fm_iob1)
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ar[18:35] <= ar[18:35] | iob[18:35];
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if(ar1_8_clr)
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ar[1:8] <= 0;
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if(ar1_8_set)
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ar[1:8] <= 8'o377;
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if(ar_fm_sc1_8J)
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ar[1:8] <= sc;
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if(ar0_5_fm_sc3_8J)
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ar[0:5] <= sc[3:8];
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|
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if(mr_clr | ar_t3)
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ar_com_cont <= 0;
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if(ar_as_t0 | ar_incdec_t0)
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ar_com_cont <= 1;
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if(ar_flag_clr) begin
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ar_pc_chg_flag <= 0;
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ar_ov_flag <= 0;
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@@ -1327,20 +1373,31 @@ module apr(
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wire fe_fm_mb0_5_1 = 0;
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reg [0:8] sc;
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wire sc_clr = 0;
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wire sc_inc = 0;
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wire sc_com = 0;
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wire sc_clr = mr_clr | cht4 | cht8a |
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fat5a | fpt3 | mst5 | dst20 |
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cht6 & ch_inc_op;
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wire sc_inc = fpt2 | fat2 | sht0 | fst1 | nrt0 |
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sct1 | mst2 | dst14a | nrt2;
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wire sc_com = cht8b | cht5 | fat3 | nrt1 | lct0 | dct0 |
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et1 & ir_fsc & ~ar[0] |
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fpt1 & fp_ar0_xor_fmf1 |
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fat0 & ~ar0_xor_mb0 |
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fpt1a & ~fp_ar0_xor_mb0_xor_fmf1 |
|
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sht1 & mb[18] |
|
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fpt1b & fp_mb0_eq_fmf1 |
|
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fat7 & mb[0] |
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nrt3 & (~ar[0] | nr_round);
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wire sc_pad = 0;
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wire sc_cry = 0;
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wire sc_fm_fe1 = 0;
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wire sc_fm_mb18_28_35_0 = 0;
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wire sc_fm_mb18_28_35_0 = et0a & (fsc | shift_op);
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wire sc_mb0_5_0_enable = 0;
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wire sc_mb6_11_1_enable = 0;
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wire sc_ar0_8_1_enable = 0;
|
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wire sc_mb0_8_1_enable = 0;
|
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// TODO: figure out what's going on here...
|
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wire sc_eq_777 = 0;
|
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wire sc0_2_eq_7 = 0;
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// TODO: what the hell is sc8b?
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wire sc_eq_777 = sc == 9'o777;
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wire sc0_2_eq_7 = sc[0:2] == 3'o7;
|
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|
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wire sat0 = 0;
|
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wire sat1 = 0;
|
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@@ -1348,9 +1405,51 @@ module apr(
|
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wire sat21 = 0;
|
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wire sat3 = 0;
|
||||
|
||||
wire sct0 = 0;
|
||||
wire sct1 = 0;
|
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wire sct2 = 0;
|
||||
wire sct0;
|
||||
wire sct1;
|
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wire sct2;
|
||||
|
||||
pa sc_pa0(.clk(clk), .reset(reset),
|
||||
.in(lct0 | dct0 | sht1 | fat5 |
|
||||
cht8b & ~ir_cao),
|
||||
.p(sct0));
|
||||
pa sc_pa1(.clk(clk), .reset(reset),
|
||||
.in((sct0_D | sct1_D) & ~sc_eq_777),
|
||||
.p(sct1));
|
||||
pa sc_pa2(.clk(clk), .reset(reset),
|
||||
.in((sct0_D | sct1_D) & sc_eq_777),
|
||||
.p(sct2));
|
||||
|
||||
wire sct0_D, sct1_D;
|
||||
dly200ns sc_dly0(.clk(clk), .reset(reset),
|
||||
.in(sct0),
|
||||
.p(sct0_D));
|
||||
// should be 75ns
|
||||
dly70ns sc_dly1(.clk(clk), .reset(reset),
|
||||
.in(sct1),
|
||||
.p(sct1_D));
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(fe_clr)
|
||||
fe <= 0;
|
||||
if(fe_fm_sc1)
|
||||
fe <= fe | sc;
|
||||
if(fe_fm_mb0_5_1)
|
||||
fe <= fe | { 3'b0, mb[0:5]};
|
||||
|
||||
if(sc_clr)
|
||||
sc <= 0;
|
||||
if(sc_inc)
|
||||
sc <= sc + 1;
|
||||
if(sc_com)
|
||||
sc <= ~sc;
|
||||
// TODO: sc_pad, sc_cry
|
||||
if(sc_fm_fe1)
|
||||
sc <= sc | fe;
|
||||
if(sc_fm_mb18_28_35_0)
|
||||
sc <= sc | ~{ mb[18], mb[28:35] };
|
||||
// TODO: single bits
|
||||
end
|
||||
|
||||
/*
|
||||
* CFAC
|
||||
@@ -1363,10 +1462,14 @@ module apr(
|
||||
wire cfac_mb_ar_swap = 0;
|
||||
wire cfac_ar_com = 0;
|
||||
wire cfac_overflow = 0;
|
||||
wire cfac_ar_sh_lt = 0;
|
||||
wire cfac_mq_sh_lt = 0;
|
||||
wire cfac_ar_sh_rt = 0;
|
||||
wire cfac_mq_sh_rt = 0;
|
||||
wire cfac_ar_sh_lt = dst14a | nrt2 |
|
||||
sct1 & (dcf1 | shift_op & ~mb[18]);
|
||||
wire cfac_mq_sh_lt = dst14a | nrt2 | dst10b |
|
||||
sct1 & (dcf1 | chf4 | shift_op & ~mb[18]);
|
||||
wire cfac_ar_sh_rt = nrt0 | mst2 | dst16 | dst10a | fdt1 |
|
||||
sct1 & (faf3 | lcf1 | shift_op & mb[18]);
|
||||
wire cfac_mq_sh_rt = nrt0 | mst2 | mst5 | fdt1 |
|
||||
sct1 & (faf3 | shift_op & mb[18]);
|
||||
|
||||
/*
|
||||
* BLT
|
||||
@@ -1462,9 +1565,31 @@ module apr(
|
||||
ir_rot | ir_rotc;
|
||||
wire sh_ac_2 = ir_ashc | ir_lshc | ir_rotc;
|
||||
|
||||
wire sht0 = 0;
|
||||
wire sht1 = 0;
|
||||
wire sht1a = 0;
|
||||
wire sht0;
|
||||
wire sht1;
|
||||
wire sht1a;
|
||||
|
||||
pa sh_p0(.clk(clk), .reset(reset),
|
||||
.in(et1 & shift_op & mb[18]),
|
||||
.p(sht0));
|
||||
pa sh_p1(.clk(clk), .reset(reset),
|
||||
.in(et3_D & shift_op),
|
||||
.p(sht1));
|
||||
pa sh_p2(.clk(clk), .reset(reset),
|
||||
.in(sct2 & shf1),
|
||||
.p(sht1a));
|
||||
|
||||
wire et3_D;
|
||||
dly100ns sh_dly(.clk(clk), .reset(reset),
|
||||
.in(et3),
|
||||
.p(et3_D));
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(mp_clr | sht1a)
|
||||
shf1 <= 0;
|
||||
if(sht1)
|
||||
shf1 <= 1;
|
||||
end
|
||||
|
||||
/*
|
||||
* MP
|
||||
@@ -1477,6 +1602,11 @@ module apr(
|
||||
wire mpt1 = 0;
|
||||
wire mpt2 = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(mp_clr | mpt0a)
|
||||
mpf1 <= 0;
|
||||
end
|
||||
|
||||
/*
|
||||
* FA
|
||||
*/
|
||||
@@ -1501,6 +1631,17 @@ module apr(
|
||||
wire fat9 = 0;
|
||||
wire fat10 = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(mp_clr | fat1b | fat10)
|
||||
faf1 <= 0;
|
||||
if(mp_clr | fat1a)
|
||||
faf2 <= 0;
|
||||
if(mp_clr | fat5a)
|
||||
faf3 <= 0;
|
||||
if(mp_clr | fat10)
|
||||
faf4 <= 0;
|
||||
end
|
||||
|
||||
/*
|
||||
* FM
|
||||
*/
|
||||
@@ -1511,6 +1652,13 @@ module apr(
|
||||
wire fmt0a = 0;
|
||||
wire fmt0b = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(mp_clr | fmt0a)
|
||||
fmf1 <= 0;
|
||||
if(mp_clr | fmt0b)
|
||||
fmf2 <= 0;
|
||||
end
|
||||
|
||||
/*
|
||||
* FD
|
||||
*/
|
||||
@@ -1522,6 +1670,13 @@ module apr(
|
||||
wire fdt0b = 0;
|
||||
wire fdt1 = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(mp_clr | fdt0a)
|
||||
fdf1 <= 0;
|
||||
if(mp_clr | fdt0b)
|
||||
fdf2 <= 0;
|
||||
end
|
||||
|
||||
/*
|
||||
* FP
|
||||
*/
|
||||
@@ -1541,6 +1696,13 @@ module apr(
|
||||
wire fpt3 = 0;
|
||||
wire fpt4 = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(mp_clr | fpt1a)
|
||||
fpf1 <= 0;
|
||||
if(mp_clr | fpt1b)
|
||||
fpf2 <= 0;
|
||||
end
|
||||
|
||||
/*
|
||||
* MS
|
||||
*/
|
||||
@@ -1555,6 +1717,11 @@ module apr(
|
||||
wire mst5 = 0;
|
||||
wire mst6 = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(mp_clr | mst3a)
|
||||
msf1 <= 0;
|
||||
end
|
||||
|
||||
/*
|
||||
* DS
|
||||
*/
|
||||
@@ -1579,6 +1746,7 @@ module apr(
|
||||
wire dst3 = 0;
|
||||
wire dst4 = 0;
|
||||
wire dst5 = 0;
|
||||
wire dst5a = 0;
|
||||
wire dst6 = 0;
|
||||
wire dst7 = 0;
|
||||
wire dst8 = 0;
|
||||
@@ -1599,12 +1767,34 @@ module apr(
|
||||
wire dst17a = 0;
|
||||
wire dst18 = 0;
|
||||
wire dst19 = 0;
|
||||
wire dst19a = 0;
|
||||
wire dst20 = 0;
|
||||
wire dst21 = 0;
|
||||
wire dst21a = 0;
|
||||
|
||||
wire ds_div_t0 = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(ds_clr | dst0a)
|
||||
dsf1 <= 0;
|
||||
if(ds_clr | dst5a)
|
||||
dsf2 <= 0;
|
||||
if(ds_clr | dst10)
|
||||
dsf3 <= 0;
|
||||
if(ds_clr | dst11a)
|
||||
dsf4 <= 0;
|
||||
if(ds_clr | dst14a)
|
||||
dsf5 <= 0;
|
||||
if(ds_clr | dst17a)
|
||||
dsf6 <= 0;
|
||||
if(mr_clr)
|
||||
dsf7 <= 0;
|
||||
if(ds_clr | dst19a)
|
||||
dsf8 <= 0;
|
||||
if(ds_clr | dst21a)
|
||||
dsf9 <= 0;
|
||||
end
|
||||
|
||||
/*
|
||||
* NR
|
||||
*/
|
||||
@@ -1627,6 +1817,15 @@ module apr(
|
||||
wire nrt5a = 0;
|
||||
wire nrt6 = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(mp_clr | nrt5a)
|
||||
nrf1 <= 0;
|
||||
if(mp_clr) begin
|
||||
nrf2 <= 0;
|
||||
nrf3 <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
/*
|
||||
* MA
|
||||
*/
|
||||
@@ -1710,6 +1909,10 @@ module apr(
|
||||
pr <= 0;
|
||||
rlr <= 0;
|
||||
end
|
||||
if(ex_set) begin
|
||||
pr <= pr | iob[0:7];
|
||||
rlr <= rlr | iob[18:25];
|
||||
end
|
||||
end
|
||||
|
||||
/*
|
||||
@@ -1926,31 +2129,82 @@ module apr(
|
||||
wire iot_outgoing = iot_datao | iot_cono;
|
||||
wire iot_status = iot_coni | iot_consz | iot_conso;
|
||||
wire iot_datai_o = iot_datai | iot_datao;
|
||||
wire iot_init_setup = 0;
|
||||
wire iot_final_setup = 0;
|
||||
wire iot_init_setup;
|
||||
wire iot_restart;
|
||||
wire iot_final_setup;
|
||||
wire iot_reset;
|
||||
|
||||
wire iot_t0 = 0;
|
||||
wire iot_t0a = 0;
|
||||
wire iot_t2 = 0;
|
||||
wire iot_t3 = 0;
|
||||
wire iot_t3a = 0;
|
||||
wire iot_t4 = 0;
|
||||
wire iot_t2;
|
||||
wire iot_t3;
|
||||
wire iot_t3a;
|
||||
wire iot_t4;
|
||||
|
||||
wire iot_go_P;
|
||||
pg iot_pg0(.clk(clk), .reset(reset),
|
||||
.in(iot_go & ~iot_reset),
|
||||
.p(iot_go_P));
|
||||
|
||||
assign iobus_iob_poweron = sw_power;
|
||||
pa iot_pa0(.clk(clk), .reset(reset),
|
||||
.in(mr_start | cpa_cono_set & iob[19]),
|
||||
.p(iobus_iob_reset));
|
||||
pa iot_pa1(.clk(clk), .reset(reset),
|
||||
.in(iot_t2 & iot_cono),
|
||||
.p(iobus_cono_clear));
|
||||
pa iot_pa2(.clk(clk), .reset(reset),
|
||||
.in(iot_t3 & iot_cono),
|
||||
.p(iobus_cono_set));
|
||||
pa iot_pa3(.clk(clk), .reset(reset),
|
||||
.in(iot_t2 & iot_datao),
|
||||
.p(iobus_datao_clear));
|
||||
pa iot_pa4(.clk(clk), .reset(reset),
|
||||
.in(iot_t3 & iot_datao),
|
||||
.p(iobus_datao_set));
|
||||
assign iobus_iob_fm_datai = iot_datai & iot_drive;
|
||||
assign iobus_iob_fm_status = iot_status & iot_drive;
|
||||
wire iob_fm_ar1 = iot_outgoing & iot_drive;
|
||||
|
||||
wire iot_t0a_D;
|
||||
dly200ns iot_dly0(.clk(clk), .reset(reset),
|
||||
.in(iot_t0a),
|
||||
.p(iot_t0a_D));
|
||||
ldly1us iot_dly1(.clk(clk), .reset(reset),
|
||||
.in(iot_go_P),
|
||||
.p(iot_t2),
|
||||
.l(iot_init_setup));
|
||||
ldly1_5us iot_dly2(.clk(clk), .reset(reset),
|
||||
.in(iot_t2),
|
||||
.p(iot_t3a),
|
||||
.l(iot_final_setup));
|
||||
ldly2us iot_dly3(.clk(clk), .reset(reset),
|
||||
.in(iot_t3a),
|
||||
.p(iot_t4),
|
||||
.l(iot_reset));
|
||||
ldly1us iot_dly4(.clk(clk), .reset(reset),
|
||||
.in(iot_t2),
|
||||
.p(iot_t3),
|
||||
.l(iot_restart));
|
||||
wire iot_drive = iot_init_setup | iot_final_setup | iot_t2;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(mr_clr | iot_t2)
|
||||
iot_go <= 0;
|
||||
if(et4 & ir_iot & ~iot_blk)
|
||||
iot_go <= 1;
|
||||
|
||||
if(mr_clr | iot_t0a)
|
||||
iot_f0a <= 0;
|
||||
if(iot_t0)
|
||||
iot_f0a <= 1;
|
||||
end
|
||||
|
||||
/* IOB */
|
||||
assign iobus_iob_poweron = 0;
|
||||
assign iobus_iob_reset = 0;
|
||||
assign iobus_datao_clear = 0;
|
||||
assign iobus_datao_set = 0;
|
||||
assign iobus_cono_clear = 0;
|
||||
assign iobus_cono_set = 0;
|
||||
assign iobus_iob_fm_datai = 0;
|
||||
assign iobus_iob_fm_status = 0;
|
||||
assign iobus_iob_out = 0;
|
||||
assign iobus_iob_out = iob_fm_ar1 ? ar :
|
||||
cpa_status ? cpa_iob :
|
||||
pi_status ? pi_iob :
|
||||
0;
|
||||
wire [0:35] iob = iobus_iob_in;
|
||||
|
||||
/*
|
||||
@@ -2038,6 +2292,8 @@ module apr(
|
||||
wire pi_sync;
|
||||
wire pi_reset;
|
||||
|
||||
wire [0:35] pi_iob = { 28'b0, pi_active, pio };
|
||||
|
||||
pa pi_pa0(.clk(clk), .reset(reset),
|
||||
.in(it0 | at0),
|
||||
.p(pi_sync));
|
||||
@@ -2082,8 +2338,9 @@ module apr(
|
||||
reg cpa_arov_enable;
|
||||
reg [33:35] cpa_pia;
|
||||
wire cpa = iobus_ios == 0;
|
||||
wire cpa_cono_set = 0;
|
||||
wire cpa_status = 0;
|
||||
wire cpa_cono_set = cpa & iobus_cono_set;
|
||||
wire cpa_status = cpa & iobus_iob_fm_status;
|
||||
wire cpa_clock_flag_set = 0;
|
||||
|
||||
wire cpa_req_enable = cpa_illeg_op | cpa_non_exist_mem | cpa_pdl_ov |
|
||||
cpa_clock_enable & cpa_clock_flag |
|
||||
@@ -2094,6 +2351,13 @@ module apr(
|
||||
for(j = 1; j <= 7; j = j + 1)
|
||||
assign cpa_req[j] = cpa_req_enable & (cpa_pia == j);
|
||||
|
||||
wire [0:35] cpa_iob = { 18'b0,
|
||||
1'b0, cpa_pdl_ov, cpa_iot_user, ex_user,
|
||||
cpa_illeg_op, cpa_non_exist_mem, 1'b0, cpa_clock_enable,
|
||||
cpa_clock_flag, 1'b0, cpa_pc_chg_enable, ar_pc_chg_flag,
|
||||
1'b0, cpa_arov_enable, ar_ov_flag,
|
||||
cpa_pia };
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(mr_start) begin
|
||||
cpa_iot_user <= 0;
|
||||
@@ -2106,6 +2370,47 @@ module apr(
|
||||
cpa_arov_enable <= 0;
|
||||
cpa_pia <= 0;
|
||||
end
|
||||
|
||||
if(cpa_cono_set & iob[21])
|
||||
cpa_iot_user <= 0;
|
||||
if(cpa_cono_set & iob[20])
|
||||
cpa_iot_user <= 1;
|
||||
|
||||
if(cpa_cono_set & iob[22])
|
||||
cpa_illeg_op <= 0;
|
||||
if(mc_illeg_address)
|
||||
cpa_illeg_op <= 1;
|
||||
|
||||
if(cpa_cono_set & iob[23])
|
||||
cpa_non_exist_mem <= 0;
|
||||
if(mc_non_exist_mem)
|
||||
cpa_non_exist_mem <= 1;
|
||||
|
||||
if(cpa_cono_set & iob[24])
|
||||
cpa_clock_enable <= 0;
|
||||
if(cpa_cono_set & iob[25])
|
||||
cpa_clock_enable <= 1;
|
||||
if(cpa_cono_set & iob[26])
|
||||
cpa_clock_flag <= 0;
|
||||
if(cpa_clock_flag_set)
|
||||
cpa_clock_flag <= 1;
|
||||
|
||||
if(cpa_cono_set & iob[27])
|
||||
cpa_pc_chg_enable <= 0;
|
||||
if(cpa_cono_set & iob[28])
|
||||
cpa_pc_chg_enable <= 1;
|
||||
if(cpa_cono_set & iob[18])
|
||||
cpa_pdl_ov <= 0;
|
||||
if(et10 & mb_ar_swap_et10 & ar_cry0)
|
||||
cpa_pdl_ov <= 1;
|
||||
|
||||
if(cpa_cono_set & iob[30])
|
||||
cpa_arov_enable <= 0;
|
||||
if(cpa_cono_set & iob[31])
|
||||
cpa_arov_enable <= 1;
|
||||
|
||||
if(cpa_cono_set)
|
||||
cpa_pia <= iob[33:35];
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -83,6 +83,21 @@ module dly50ns(input clk, input reset, input in, output p);
|
||||
assign p = r == 7;
|
||||
endmodule
|
||||
|
||||
module dly70ns(input clk, input reset, input in, output p);
|
||||
reg [3:0] r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if(reset)
|
||||
r <= 0;
|
||||
else begin
|
||||
if(r)
|
||||
r <= r + 1;
|
||||
if(in)
|
||||
r <= 1;
|
||||
end
|
||||
end
|
||||
assign p = r == 9;
|
||||
endmodule
|
||||
|
||||
module dly100ns(input clk, input reset, input in, output p);
|
||||
reg [3:0] r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
@@ -188,6 +203,75 @@ module dly1us(input clk, input reset, input in, output p);
|
||||
assign p = r == 102;
|
||||
endmodule
|
||||
|
||||
module ldly1us(input clk, input reset, input in, output p, output l);
|
||||
reg [6:0] r;
|
||||
reg l;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if(reset) begin
|
||||
l <= 0;
|
||||
r <= 0;
|
||||
end else begin
|
||||
if(r)
|
||||
r <= r + 1;
|
||||
if(in) begin
|
||||
l <= 1;
|
||||
r <= 1;
|
||||
end
|
||||
if(r == 101) begin
|
||||
l <= 0;
|
||||
//r <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
assign p = r == 102;
|
||||
endmodule
|
||||
|
||||
module ldly1_5us(input clk, input reset, input in, output p, output l);
|
||||
reg [7:0] r;
|
||||
reg l;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if(reset) begin
|
||||
l <= 0;
|
||||
r <= 0;
|
||||
end else begin
|
||||
if(r)
|
||||
r <= r + 1;
|
||||
if(in) begin
|
||||
l <= 1;
|
||||
r <= 1;
|
||||
end
|
||||
if(r == 151) begin
|
||||
l <= 0;
|
||||
//r <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
assign p = r == 152;
|
||||
endmodule
|
||||
|
||||
module ldly2us(input clk, input reset, input in, output p, output l);
|
||||
reg [7:0] r;
|
||||
reg l;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if(reset) begin
|
||||
l <= 0;
|
||||
r <= 0;
|
||||
end else begin
|
||||
if(r)
|
||||
r <= r + 1;
|
||||
if(in) begin
|
||||
l <= 1;
|
||||
r <= 1;
|
||||
end
|
||||
if(r == 201) begin
|
||||
l <= 0;
|
||||
//r <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
assign p = r == 202;
|
||||
endmodule
|
||||
|
||||
module dly100us(input clk, input reset, input in, output p);
|
||||
reg [15:0] r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
|
||||
@@ -1,15 +1,15 @@
|
||||
[*]
|
||||
[*] GTKWave Analyzer v3.3.76 (w)1999-2016 BSI
|
||||
[*] Wed Nov 16 16:03:38 2016
|
||||
[*] Sun Nov 20 23:19:44 2016
|
||||
[*]
|
||||
[dumpfile] "/home/aap/src/pdp6/verilog/dump.vcd"
|
||||
[dumpfile_mtime] "Wed Nov 16 16:02:55 2016"
|
||||
[dumpfile_size] 275421
|
||||
[dumpfile_mtime] "Sun Nov 20 15:05:49 2016"
|
||||
[dumpfile_size] 137687
|
||||
[savefile] "/home/aap/src/pdp6/verilog/test.gtkw"
|
||||
[timestart] 5380
|
||||
[timestart] 4220
|
||||
[size] 1920 1080
|
||||
[pos] -1 -1
|
||||
*-11.385187 13535 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
*-7.832355 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] test.
|
||||
[treeopen] test.pdp6.
|
||||
[treeopen] test.pdp6.mem0.
|
||||
@@ -129,11 +129,14 @@ test.pdp6.apr0.mc_illeg_address
|
||||
test.pdp6.apr0.mc_membus_fm_mb1
|
||||
@200
|
||||
-
|
||||
@30
|
||||
test.pdp6.apr0.rlr[18:25]
|
||||
test.pdp6.apr0.rla[18:25]
|
||||
test.pdp6.apr0.pr[18:25]
|
||||
@28
|
||||
test.pdp6.apr0.ex_clr
|
||||
test.pdp6.apr0.ex_set
|
||||
test.pdp6.apr0.rlr[18:25]
|
||||
@30
|
||||
test.pdp6.apr0.rla[18:25]
|
||||
@28
|
||||
test.pdp6.apr0.pr[18:25]
|
||||
test.pdp6.apr0.pr18_ok
|
||||
@200
|
||||
-
|
||||
@@ -147,7 +150,7 @@ test.pdp6.apr0.mc_split_cyc_sync
|
||||
test.pdp6.apr0.mc_mb_membus_enable
|
||||
@1401200
|
||||
-MC
|
||||
@c00201
|
||||
@c00200
|
||||
-I A
|
||||
@28
|
||||
test.pdp6.apr0.it0
|
||||
@@ -164,7 +167,7 @@ test.pdp6.apr0.at3a
|
||||
test.pdp6.apr0.af3a
|
||||
test.pdp6.apr0.at4
|
||||
test.pdp6.apr0.at5
|
||||
@1401201
|
||||
@1401200
|
||||
-I A
|
||||
@c00200
|
||||
-F
|
||||
@@ -191,7 +194,7 @@ test.pdp6.apr0.ft6a
|
||||
test.pdp6.apr0.ft7
|
||||
@1401200
|
||||
-F
|
||||
@800200
|
||||
@c00200
|
||||
-E
|
||||
@28
|
||||
test.pdp6.apr0.et0a
|
||||
@@ -205,9 +208,9 @@ test.pdp6.apr0.et7
|
||||
test.pdp6.apr0.et8
|
||||
test.pdp6.apr0.et9
|
||||
test.pdp6.apr0.et10
|
||||
@1000200
|
||||
@1401200
|
||||
-E
|
||||
@800200
|
||||
@c00200
|
||||
-S
|
||||
@28
|
||||
test.pdp6.apr0.s_ac_0
|
||||
@@ -224,7 +227,7 @@ test.pdp6.apr0.st5a
|
||||
test.pdp6.apr0.st6
|
||||
test.pdp6.apr0.sf7
|
||||
test.pdp6.apr0.st7
|
||||
@1000200
|
||||
@1401200
|
||||
-S
|
||||
@c00200
|
||||
-iobus
|
||||
@@ -343,9 +346,48 @@ test.pdp6.apr0.pi_req[1:7]
|
||||
test.pdp6.apr0.pih[1:7]
|
||||
test.pdp6.apr0.pir[1:7]
|
||||
test.pdp6.apr0.pio[1:7]
|
||||
test.pdp6.apr0.pi_select
|
||||
@30
|
||||
test.pdp6.apr0.pi_iob[0:35]
|
||||
@28
|
||||
test.pdp6.apr0.iob_pi_req[1:7]
|
||||
@1401200
|
||||
-PI
|
||||
@c00200
|
||||
-IOT
|
||||
@28
|
||||
test.pdp6.apr0.iot_go
|
||||
test.pdp6.apr0.iot_go_P
|
||||
@200
|
||||
-
|
||||
@28
|
||||
test.pdp6.apr0.iot_t0
|
||||
test.pdp6.apr0.iot_f0a
|
||||
test.pdp6.apr0.iot_t0a
|
||||
test.pdp6.apr0.iot_init_setup
|
||||
test.pdp6.apr0.iot_t2
|
||||
test.pdp6.apr0.iot_final_setup
|
||||
test.pdp6.apr0.iot_drive
|
||||
test.pdp6.apr0.iot_t3a
|
||||
test.pdp6.apr0.iot_reset
|
||||
test.pdp6.apr0.iot_t4
|
||||
test.pdp6.apr0.iot_t3
|
||||
test.pdp6.apr0.iot_restart
|
||||
@200
|
||||
-
|
||||
@28
|
||||
test.pdp6.apr0.iot_blki
|
||||
test.pdp6.apr0.iot_datai
|
||||
test.pdp6.apr0.iot_blko
|
||||
test.pdp6.apr0.iot_datao
|
||||
test.pdp6.apr0.iot_coni
|
||||
test.pdp6.apr0.iot_cono
|
||||
test.pdp6.apr0.iot_consz
|
||||
test.pdp6.apr0.iot_conso
|
||||
@1401200
|
||||
-IOT
|
||||
@800200
|
||||
-misc
|
||||
@28
|
||||
test.pdp6.apr0.ar_com_cont
|
||||
test.pdp6.apr0.ar_add
|
||||
@@ -365,5 +407,35 @@ test.pdp6.apr0.pc_inc_et9
|
||||
test.pdp6.apr0.pc_inc_inh_et0
|
||||
test.pdp6.apr0.pc_set_OR_pc_inc
|
||||
test.pdp6.apr0.pc_set_enable
|
||||
@1000200
|
||||
-misc
|
||||
@c00200
|
||||
-cpa
|
||||
@28
|
||||
test.pdp6.apr0.cpa
|
||||
test.pdp6.apr0.cpa_cono_set
|
||||
test.pdp6.apr0.cpa_status
|
||||
@200
|
||||
-
|
||||
@28
|
||||
test.pdp6.apr0.cpa_iot_user
|
||||
test.pdp6.apr0.cpa_illeg_op
|
||||
test.pdp6.apr0.cpa_non_exist_mem
|
||||
test.pdp6.apr0.cpa_clock_enable
|
||||
test.pdp6.apr0.cpa_clock_flag
|
||||
test.pdp6.apr0.cpa_pc_chg_enable
|
||||
test.pdp6.apr0.cpa_pdl_ov
|
||||
test.pdp6.apr0.cpa_arov_enable
|
||||
test.pdp6.apr0.cpa_pia[33:35]
|
||||
@30
|
||||
test.pdp6.apr0.cpa_iob[0:35]
|
||||
@200
|
||||
-
|
||||
@28
|
||||
test.pdp6.apr0.iob_pi_req[1:7]
|
||||
test.pdp6.apr0.iobus_pi_req[1:7]
|
||||
test.pdp6.apr0.cpa_req[1:7]
|
||||
@1401200
|
||||
-cpa
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
|
||||
@@ -18,17 +18,31 @@ endmodule
|
||||
module test;
|
||||
wire clk;
|
||||
reg reset;
|
||||
reg stop;
|
||||
|
||||
clock clock0(clk);
|
||||
pdp6 pdp6(.clk(clk), .reset(reset));
|
||||
|
||||
initial begin
|
||||
// #110000 $finish;
|
||||
#20000 $finish;
|
||||
stop = 0;
|
||||
// #110000 stop = 1;
|
||||
#20000 stop = 1;
|
||||
end
|
||||
always @(pdp6.apr0.st7)
|
||||
if(pdp6.apr0.st7)
|
||||
stop = 1;
|
||||
|
||||
// dump memory on exit
|
||||
always @(stop)
|
||||
if(stop) begin: fin
|
||||
integer i;
|
||||
for(i = 0; i < 'o50; i = i + 1)
|
||||
if(i < 'o20)
|
||||
$display("%o %o %o", i, pdp6.mem0.core[i], pdp6.fmem0.ff[i]);
|
||||
else
|
||||
$display("%o %o", i, pdp6.mem0.core[i]);
|
||||
$finish;
|
||||
end
|
||||
|
||||
initial begin
|
||||
#100 `TESTKEY = 1;
|
||||
@@ -43,15 +57,38 @@ module test;
|
||||
|
||||
initial begin
|
||||
#400;
|
||||
pdp6.apr0.cpa_pia = 5;
|
||||
/*
|
||||
pdp6.apr0.pio = 7'b1111111;
|
||||
// pdp6.apr0.cpa_pia = 5;
|
||||
pdp6.apr0.pio = 7'b1111100;
|
||||
pdp6.apr0.pir = 7'b0000000;
|
||||
pdp6.apr0.pih = 7'b0000100;
|
||||
#10;
|
||||
pdp6.apr0.pi_active = 1;
|
||||
*/
|
||||
end
|
||||
// assign pdp6.apr0.iobus_pi_req = 0;
|
||||
assign pdp6.apr0.iobus_pi_req = 7'b0010000;
|
||||
// assign pdp6.apr0.iobus_pi_req = 7'b0010000;
|
||||
assign pdp6.apr0.iobus_pi_req = 0;
|
||||
|
||||
/*
|
||||
initial begin
|
||||
#300;
|
||||
pdp6.apr0.cpa_iot_user <= 1;
|
||||
#20;
|
||||
pdp6.apr0.cpa_illeg_op <= 1;
|
||||
#20;
|
||||
pdp6.apr0.cpa_non_exist_mem <= 1;
|
||||
#20;
|
||||
pdp6.apr0.cpa_clock_enable <= 1;
|
||||
#20;
|
||||
pdp6.apr0.cpa_clock_flag <= 1;
|
||||
#20;
|
||||
pdp6.apr0.cpa_pc_chg_enable <= 1;
|
||||
#20;
|
||||
pdp6.apr0.cpa_pdl_ov <= 1;
|
||||
#20;
|
||||
pdp6.apr0.cpa_arov_enable <= 1;
|
||||
#20;
|
||||
pdp6.apr0.cpa_pia <= 7;
|
||||
end
|
||||
*/
|
||||
|
||||
/* initial begin
|
||||
#100;
|
||||
@@ -110,43 +147,53 @@ module test;
|
||||
|
||||
end
|
||||
|
||||
/*
|
||||
initial begin
|
||||
#80 pdp6.apr0.pr = 8'o003;
|
||||
pdp6.apr0.rlr = 8'o002;
|
||||
//pdp6.apr0.ex_user = 1;
|
||||
end
|
||||
*/
|
||||
|
||||
initial begin
|
||||
#1 reset = 1;
|
||||
#20 reset = 0;
|
||||
|
||||
pdp6.datasw = 36'o111777222666;
|
||||
// pdp6.mas = 18'o010100;
|
||||
// pdp6.mas = 18'o000004;
|
||||
pdp6.mas = 18'o000023;
|
||||
//pdp6.mas = 18'o777777;
|
||||
pdp6.mas = 18'o000034;
|
||||
|
||||
pdp6.fmem0.ff['o0] = 36'o000000_010000;
|
||||
pdp6.fmem0.ff['o1] = 36'o000000_000222;
|
||||
pdp6.fmem0.ff['o2] = 36'o700000_000006;
|
||||
pdp6.fmem0.ff['o1] = 36'o000000_010222;
|
||||
pdp6.fmem0.ff['o2] = 36'o700000_200006;
|
||||
pdp6.fmem0.ff['o3] = 36'o500000_000004;
|
||||
pdp6.fmem0.ff['o4] = 36'o000000_010304;
|
||||
pdp6.fmem0.ff['o5] = 36'o377777_777777;
|
||||
// MOVE 1,@104(4) FAC_INH
|
||||
pdp6.mem0.core['o20] = 36'o200_064_000104;
|
||||
// MOVEM 1,@104(4)
|
||||
pdp6.mem0.core['o21] = 36'o202_064_000104;
|
||||
// ROTC 2,3
|
||||
pdp6.mem0.core['o22] = 36'o245_100_000003;
|
||||
pdp6.fmem0.ff['o6] = 36'o444000_222000;
|
||||
pdp6.fmem0.ff['o17] = 36'o777000_001000; // PDL ptr
|
||||
// pdp6.fmem0.ff['o17] = 36'o777000_777777; // PDL ptr
|
||||
pdp6.mem0.core['o20] = 36'o200_064_000104; // MOVE 1,@104(4) FAC_INH
|
||||
pdp6.mem0.core['o21] = 36'o202_064_000104; // MOVEM 1,@104(4)
|
||||
pdp6.mem0.core['o22] = 36'o245_100_000003; // ROTC 2,3
|
||||
pdp6.mem0.core['o23] = 36'o700200_675550; // CONO APR,675550
|
||||
pdp6.mem0.core['o24] = 36'o700200_102227; // CONO APR,102227
|
||||
pdp6.mem0.core['o25] = 36'o700240_000005; // CONI APR,5
|
||||
pdp6.mem0.core['o26] = 36'o700140_000006; // DATAO APR,6
|
||||
pdp6.mem0.core['o27] = 36'o700040_000005; // DATAI APR,5
|
||||
pdp6.mem0.core['o30] = 36'o700640_000005; // CONI APR,5
|
||||
pdp6.mem0.core['o31] = 36'o260740_000020; // PUSHJ 17,20
|
||||
pdp6.mem0.core['o31] = 36'o250040_000000; // AOS 1,
|
||||
pdp6.mem0.core['o32] = 36'o270000_000001; // ADD 0,1
|
||||
pdp6.mem0.core['o33] = 36'o274000_000001; // SUB 0,1
|
||||
|
||||
pdp6.mem0.core['o23] = 36'o700200_000005;
|
||||
pdp6.mem0.core['o34] = 36'o245_100_000003; // ROTC 2,3
|
||||
pdp6.mem0.core['o35] = 36'o245_100_777775; // ROTC 2,-3
|
||||
pdp6.mem0.core['o36] = 36'o244_100_000001; // ASHC 2,1
|
||||
|
||||
pdp6.mem0.core['o10410] = 36'o000_000_000333;
|
||||
end
|
||||
|
||||
initial begin
|
||||
#25 pdp6.sw_power = 1;
|
||||
#25 pdp6.sw_power = 0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
Reference in New Issue
Block a user