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140 lines
2.5 KiB
Verilog
Executable File
140 lines
2.5 KiB
Verilog
Executable File
// input 50mhz, output ~60hz
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module clk60hz(
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input wire clk,
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output wire outclk
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);
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reg [19:0] cnt = 0;
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assign outclk = cnt == 833333;
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always @(posedge clk)
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if(outclk)
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cnt <= 0;
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else
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cnt <= cnt + 20'b1;
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endmodule
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// input 50mhz, output 63.3hz
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module clk63_3hz(
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input wire clk,
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output wire outclk
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);
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reg [19:0] cnt = 0;
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assign outclk = cnt == 789900;
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always @(posedge clk)
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if(outclk)
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cnt <= 0;
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else
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cnt <= cnt + 20'b1;
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endmodule
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// input 50mhz, output 25khz
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module clk25khz(
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input wire clk,
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input wire en,
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output wire outclk
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);
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reg [10:0] cnt = 0;
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assign outclk = en & (cnt == 2000);
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always @(posedge clk)
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if(outclk)
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cnt <= 0;
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else
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cnt <= cnt + 11'b1;
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endmodule
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// input 50mhz, output 50khz
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module clk50khz(
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input wire clk,
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output wire outclk
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);
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reg [9:0] cnt = 0;
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assign outclk = cnt == 1000;
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always @(posedge clk)
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if(outclk)
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cnt <= 0;
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else
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cnt <= cnt + 10'b1;
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endmodule
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module pg(
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input clk,
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input reset,
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input in,
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output p
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);
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reg [1:0] x;
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always @(posedge clk or posedge reset)
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if(reset)
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x <= 0;
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else
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x <= { x[0], in };
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assign p = x[0] & !x[1];
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endmodule
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/*
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// This breaks things because it doesn't detect power on
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module pg(input wire clk, input wire reset, input wire in, output wire p);
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reg [1:0] x;
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reg [1:0] init = 0;
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always @(posedge clk or posedge reset)
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if(reset)
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init <= 0;
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else begin
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x <= { x[0], in };
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init <= { init[0], 1'b1 };
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end
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assign p = (&init) & x[0] & !x[1];
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endmodule
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*/
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module pa(input wire clk, input wire reset, input wire in, output wire p);
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reg [1:0] x;
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reg [1:0] init = 0;
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always @(posedge clk or posedge reset)
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if(reset)
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init <= 0;
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else begin
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x <= { x[0], in };
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init <= { init[0], 1'b1 };
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end
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assign p = (&init) & x[0] & !x[1];
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endmodule
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// TODO: check the purpose of these
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/* "bus driver", 40ns delayed pulse */
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module bd(input clk, input reset, input in, output p);
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reg [2:0] r;
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always @(posedge clk or posedge reset) begin
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if(reset)
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r <= 0;
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else begin
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if(r)
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r <= r + 3'b1;
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if(in)
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r <= 1;
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end
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end
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assign p = r == 2;
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endmodule
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/* Same as above but with longer pulse. Used to pulse mb
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* because one more clock cycle is needed to get the data
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* after the pulse has been synchronized. */
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// TODO? get rid of this and just latch
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module bd2(input clk, input reset, input in, output p);
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reg [2:0] r;
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always @(posedge clk or posedge reset) begin
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if(reset)
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r <= 0;
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else begin
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if(r)
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r <= r + 3'b1;
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if(in)
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r <= 1;
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end
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end
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assign p = r == 2 || r == 3 || r == 4 || r == 5;
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endmodule
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