1
0
mirror of https://github.com/antonblanchard/chiselwatt.git synced 2026-01-14 07:40:37 +00:00

Buffer divide final formatting

Add an extra cycle to the divider that buffers the final formatting.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard 2020-02-06 21:50:23 +11:00 committed by Anton Blanchard
parent cdb995c6e1
commit 4ebe7adf28

View File

@ -71,14 +71,15 @@ class SimpleDivider(val bits: Int) extends Module {
overflow := quotient(63, 31).orR
}
io.out.bits := quotient
val result = WireDefault(quotient)
when (overflow) {
io.out.bits := 0.U
result := 0.U
} .elsewhen (is32bit && !modulus) {
io.out.bits := 0.U(32.W) ## quotient(31, 0)
result := 0.U(32.W) ## quotient(31, 0)
}
io.out.valid := (count === (bits+1).U) && busy
io.out.bits := RegNext(result)
io.out.valid := RegNext((count === (bits+1).U) && busy)
when (io.out.valid) {
busy := false.B
}