mirror of
https://github.com/antonblanchard/chiselwatt.git
synced 2026-01-14 07:40:37 +00:00
Anton Blanchard
GitHub
commit
5abdf7ce5c
4
Makefile
4
Makefile
@ -68,8 +68,8 @@ OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
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synth: chiselwatt.bit
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chiselwatt.json: $(verilog_files) insns.hex pll_ecp5_evn.v toplevel.v
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$(YOSYS) -p "read_verilog -sv pll_ecp5_evn.v toplevel.v Core.v MemoryBlackBox.v; synth_ecp5 -json $@ -top toplevel"
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chiselwatt.json: $(verilog_files) insns.hex pll/pll_ehxplll.v toplevel.v
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$(YOSYS) -p "read_verilog -sv pll/pll_ehxplll.v toplevel.v Core.v MemoryBlackBox.v; synth_ecp5 -json $@ -top toplevel"
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chiselwatt_out.config: chiselwatt.json $(LPF)
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$(NEXTPNR) --json $< --lpf $(LPF) --textcfg $@ $(NEXTPNR_FLAGS) --package $(PACKAGE)
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45
chiselwatt.core
Normal file
45
chiselwatt.core
Normal file
@ -0,0 +1,45 @@
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CAPI=2:
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name : ::chiselwatt:0
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filesets:
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core:
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files:
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- Core.v
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- MemoryBlackBox.v
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- toplevel.v
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- insns.hex : {copyto : insns.hex, file_type : user}
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file_type : verilogSource
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cmod_a7-35:
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files:
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- constraints/cmod_a7-35.xdc : {file_type : xdc}
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- pll/pll_mmcme2.v : {file_type : verilogSource}
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ecp5-evn:
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files:
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- constraints/ecp5-evn.lpf : {file_type : LPF}
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- pll/pll_ehxplll.v : {file_type : verilogSource}
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targets:
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cmod_a7-35:
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default_tool: vivado
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filesets: [core, cmod_a7-35]
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parameters :
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- RESET_LOW=false
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tools:
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vivado: {part : xc7a35tcpg236-1}
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toplevel : toplevel
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ecp5-evn:
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default_tool: diamond
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filesets: [core, ecp5-evn]
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tools:
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diamond: {part: LFE5U-85F-8BG381I}
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toplevel : toplevel
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parameters:
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RESET_LOW:
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datatype : bool
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description : External reset button polarity
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paramtype : generic
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20
constraints/cmod_a7-35.xdc
Normal file
20
constraints/cmod_a7-35.xdc
Normal file
@ -0,0 +1,20 @@
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## Clock signal 12 MHz
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set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { clock }];
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create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {clock}];
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set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { io_tx }];
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set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { io_rx }];
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set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { reset }];
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set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports { io_terminate }];
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set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { io_ledB }];
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set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { io_ledC }];
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property CFGBVS VCCO [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
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set_property CONFIG_MODE SPIx4 [current_design]
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12
pll/pll_bypass.v
Normal file
12
pll/pll_bypass.v
Normal file
@ -0,0 +1,12 @@
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module pll(
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input clki,
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output clko,
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output lock
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);
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always @* begin
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lock <= 1;
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clko <= clki;
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end
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endmodule
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36
pll/pll_ehxplll.v
Normal file
36
pll/pll_ehxplll.v
Normal file
@ -0,0 +1,36 @@
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module pll(
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input clki,
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output clko,
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output lock
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);
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(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
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EHXPLLL #(
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.PLLRST_ENA("DISABLED"),
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.INTFB_WAKE("DISABLED"),
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.STDBY_ENABLE("DISABLED"),
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.DPHASE_SOURCE("DISABLED"),
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.CLKOP_FPHASE(0),
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.CLKOP_CPHASE(11),
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.OUTDIVIDER_MUXA("DIVA"),
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.CLKOP_ENABLE("ENABLED"),
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.CLKOP_DIV(12),
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.CLKFB_DIV(25),
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.CLKI_DIV(6),
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.FEEDBK_PATH("CLKOP")
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) pll_i (
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.CLKI(clki),
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.CLKFB(clko),
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.CLKOP(clko),
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.LOCK(lock),
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.RST(1'b0),
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.STDBY(1'b0),
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.PHASESEL0(1'b0),
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.PHASESEL1(1'b0),
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.PHASEDIR(1'b0),
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.PHASESTEP(1'b0),
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.PLLWAKESYNC(1'b0),
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.ENCLKOP(1'b0)
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);
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endmodule
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26
pll/pll_mmcme2.v
Normal file
26
pll/pll_mmcme2.v
Normal file
@ -0,0 +1,26 @@
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module pll(
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input clki,
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output clko,
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output lock
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);
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wire clkfb;
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MMCME2_BASE #(
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.BANDWIDTH("OPTIMIZED"),
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.CLKFBOUT_MULT_F(50.0),
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.CLKIN1_PERIOD(83.33),
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.CLKOUT0_DIVIDE_F(12.0),
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.DIVCLK_DIVIDE(1),
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.STARTUP_WAIT("FALSE")
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) MMCME2_BASE_inst (
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.CLKOUT0(clko),
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.CLKFBOUT(clkfb),
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.LOCKED(lock),
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.CLKIN1(clki),
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.PWRDWN(1'b0),
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.RST(1'b0),
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.CLKFBIN(clkfb)
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);
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endmodule
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@ -1,30 +0,0 @@
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module pll_ecp5_evn(input clki, output clko, output lock);
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(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
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EHXPLLL #(
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.PLLRST_ENA("DISABLED"),
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.INTFB_WAKE("DISABLED"),
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.STDBY_ENABLE("DISABLED"),
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.DPHASE_SOURCE("DISABLED"),
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.CLKOP_FPHASE(0),
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.CLKOP_CPHASE(11),
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.OUTDIVIDER_MUXA("DIVA"),
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.CLKOP_ENABLE("ENABLED"),
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.CLKOP_DIV(12),
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.CLKFB_DIV(25),
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.CLKI_DIV(6),
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.FEEDBK_PATH("CLKOP")
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) pll_i (
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.CLKI(clki),
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.CLKFB(clko),
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.CLKOP(clko),
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.LOCK(lock),
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.RST(1'b0),
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.STDBY(1'b0),
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.PHASESEL0(1'b0),
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.PHASESEL1(1'b0),
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.PHASEDIR(1'b0),
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.PHASESTEP(1'b0),
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.PLLWAKESYNC(1'b0),
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.ENCLKOP(1'b0)
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);
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endmodule
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74
toplevel.v
74
toplevel.v
@ -1,47 +1,45 @@
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module toplevel(
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input clock,
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input reset,
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output io_tx,
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input io_rx,
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output io_terminate,
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output io_ledB,
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output io_ledC
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module toplevel #(
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parameter RESET_LOW = 1
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) (
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input clock,
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input reset,
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output io_tx,
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input io_rx,
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output io_terminate,
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output io_ledB,
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output io_ledC
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);
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wire clock_out;
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reg reset_out;
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wire lock;
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wire clock_out;
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reg reset_out;
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wire lock;
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pll_ecp5_evn pll(
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.clki(clock),
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.clko(clock_out),
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.lock(lock)
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);
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pll chiselwatt_pll(
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.clki(clock),
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.clko(clock_out),
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.lock(lock)
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);
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Core core(
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.clock(clock_out),
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.reset(reset_out),
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.io_tx(io_tx),
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.io_rx(io_rx),
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.io_terminate(io_terminate),
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.io_ledB(io_ledB),
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.io_ledC(io_ledC)
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);
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Core core(
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.clock(clock_out),
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.reset(reset_out),
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.io_tx(io_tx),
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.io_rx(io_rx),
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.io_terminate(io_terminate),
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.io_ledB(io_ledB),
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.io_ledC(io_ledC)
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);
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reg [21:0] cnt = ~0;
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reg [21:0] cnt = ~0;
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always@(posedge clock)
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begin
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if (~lock || ~reset)
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begin
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cnt <= ~0;
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end
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else if (cnt != 0)
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begin
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cnt <= cnt - 1;
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end
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always@(posedge clock) begin
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if (~lock || (reset ^ RESET_LOW)) begin
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cnt <= ~0;
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end else if (cnt != 0) begin
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cnt <= cnt - 1;
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end
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reset_out <= |cnt;
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end
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reset_out <= |cnt;
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end
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endmodule
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