1
0
mirror of https://github.com/antonblanchard/chiselwatt.git synced 2026-01-13 23:37:16 +00:00

Fix typo in toplevel signal name

I must have screwed this up when adding the PLL. It's surprising
that yosys didn't complain.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard 2020-01-30 07:56:24 +11:00 committed by Anton Blanchard
parent 729c02c8c9
commit 755c90b4fa

View File

@ -8,7 +8,7 @@ module toplevel(
output io_ledC
);
wire clk_out;
wire clock_out;
wire reset_out;
wire lock;