Merge pull request #44 from carlosedp/readme-samples

Improve readme with Fusesoc info and update samples

Makefile

@@ -119,20 +119,26 @@ apps_dir = ./samples
 
 hello_world:
 	docker run -it --rm -w /build -v $(PWD):/build carlosedp/crossbuild-ppc64le make -C $(apps_dir)/hello_world
-	@scripts/bin2hex.py $(apps_dir)/hello_world/hello_world.bin > ./insns.hex
+	@cp -R $(apps_dir)/hello_world/hello_world.elf $(apps_dir)/binaries/hello_world
+	@cp -R $(apps_dir)/hello_world/hello_world.bin $(apps_dir)/binaries/hello_world
+	@scripts/bin2hex.py $(apps_dir)/binaries/hello_world/hello_world.bin > $(apps_dir)/binaries/hello_world/hello_world.hex
+	@ln -sf $(apps_dir)/binaries/hello_world/hello_world.hex ./insns.hex
 
 micropython:
-	@if [ ! -d "$(apps_dir)/micropyton/ports/powerpc" ] ; then \
-		rm -rf $(apps_dir)/micropyton; \
-		echo "Cloning micropython repo into $(apps_dir)/micropyton"; \
-		git clone https://github.com/micropython/micropython.git $(apps_dir)/micropyton; \
+	@if [ ! -d "$(apps_dir)/micropython/ports/powerpc" ] ; then \
+		rm -rf $(apps_dir)/micropython; \
+		echo "Cloning micropython repo into $(apps_dir)/micropython"; \
+		git clone https://github.com/micropython/micropython.git $(apps_dir)/micropython; \
 	else \
 		echo "Micropython repo exists, updating..."; \
-		cd "$(apps_dir)/micropyton"; \
+		pushd "$(apps_dir)/micropython"; \
 		git pull; \
+		popd; \
 	fi
-	@docker run -it --rm -v $(PWD):/build carlosedp/crossbuild-ppc64le make -C $(apps_dir)/micropyton/ports/powerpc
-	@scripts/bin2hex.py $(apps_dir)/micropyton/ports/powerpc/build/firmware.bin > ./insns.hex
+	@docker run -it --rm -v $(PWD):/build carlosedp/crossbuild-ppc64le make -C $(apps_dir)/micropython/ports/powerpc
+	@cp $(apps_dir)/micropython/ports/powerpc/build/firmware.bin $(apps_dir)/binaries/micropython
+	@cp $(apps_dir)/micropython/ports/powerpc/build/firmware.elf $(apps_dir)/binaries/micropython
+	@scripts/bin2hex.py $(apps_dir)/binaries/micropython/firmware.bin > $(apps_dir)/binaries/micropython/firmware.hex
 
 clean:
 	@rm -f Core.fir firrtl_black_box_resource_files.f Core.v Core.anno.json MemoryBlackBox.v

README.md

@@ -41,29 +41,72 @@ make dockerlator
 exit
 ```
 
-## Synthesizing for FPGAs using Open Source tools (yosys/nextpnr)
+## Synthesizing for FPGAs
 
-Synthesis on FPGAs is supported with yosys/nextpnr. At the moment the tools support
-Lattice ECP5 FPGAs. The build process uses Docker images, so no software other
-than Docker needs to be installed. If you prefer podman you can use that too,
-just adjust it in `Makefile`, `DOCKER=podman`.
+Synthesis on FPGAs is supported with [Fusesoc](https://github.com/olofk/fusesoc) to enable multiple targets and EDA backends. Fusesoc works with Edalize to provide package management and backend build for multiple FPGA vendors. At the moment the Chiselwatt supports some Xilinx, Lattice and Microchip FPGAs.
 
-### hello_world
+There is also a  build process using Makefiles and Docker images, so no software other than Docker needs to be installed. If you prefer podman you can use that too, just adjust it in `Makefile`, `DOCKER=podman`.
+
+### Using Fusesoc
+
+Install Fusesoc with Python3 pip:
+
+```sh
+pip3 install fusesoc
+```
+
+Create a workspace and add Chiselwatt as a library:
+
+```sh
+mkdir workspace
+cd workspace
+
+fusesoc library add chiselwatt https://github.com/antonblanchard/chiselwatt
+
+fusesoc core list
+```
+
+Show all available targets:
+
+```sh
+fusesoc core show chiselwatt
+```
+
+Adjust memory requirements:
 
 The `hello_world` example should run everywhere, so start with it.
 Edit `src/main/scala/Core.scala` and set memory to 16 kB (`16*1024`):
 
 ```scala
-  (new ChiselStage).emitVerilog(new Core(64, 16*1024, "insns.hex", 0x0))
+  (new ChiselStage).emitVerilog(new Core(64, 16*1024, "insns.hex", 0x0, 50000000))
 ```
 
-Then link in the hello_world image:
+Build Chiselwatt (using mill, requires Java):
+
+```sh
+pushd fusesoc_libraries/chiselwatt
+# Link Hello World sample application
+ln -sf ./samples/binaries/hello_world/hello_world.hex ./insns.hex
+make
+popd
+
+# Build the project files for your target
+fusesoc run --target=polarfireeval_es chiselwatt
+```
+
+If you have the EDA tools installed, your core will be built, otherwise the project files will be placed in `build` directory.
+
+Some FPGA's, mainly Lattice using Yosys/NextPNR have a memory synthesys issue that restricts the use of Micropython.[see  here](#Micropython).
+
+### Using the Makefile to build using Open Source tools (yosys/nextpnr)
+
+Link in the hello_world image:
 
 ```sh
 ln -s samples/binaries/hello_world/hello_world.hex insns.hex
 ```
 
-### Building and programming the FPGA
+#### Building and programming the FPGA
 
 The `Makefile` currently supports the following FPGA boards by defining the `ECP5_BOARD` parameter on make:
 
@@ -96,7 +139,7 @@ After programming, if you connect to the serial port of the FPGA at 115200 8n1,
 and after that all input will be echoed to the output. On Linux, picocom can be used.
 Another option below is a simple python script.
 
-### Micropython
+#### Micropython
 
 Unfortunately due to an issue in yosys/nextpnr, dual port RAMs are not
 working. More details can be found in <https://github.com/YosysHQ/yosys/issues/1101>.

samples/Dockerfile.crossbuild-ppc64le

@@ -1,8 +1,8 @@
 # build with docker build -t REPO/crossbuild-ppc64le -f Dockerfile.crossbuild-ppc64le .
-FROM debian:buster
+FROM python:3-buster
 
 ENV DEBIAN_FRONTEND noninteractive
-ENV TOOLCHAIN_URL https://toolchains.bootlin.com/downloads/releases/toolchains/powerpc64le-power8/tarballs/powerpc64le-power8--glibc--bleeding-edge-2020.02-2.tar.bz2
+ENV TOOLCHAIN_URL https://toolchains.bootlin.com/downloads/releases/toolchains/powerpc64le-power8/tarballs/powerpc64le-power8--glibc--bleeding-edge-2020.08-1.tar.bz2
 
 RUN apt-get update && \
     apt-get install -y --no-install-recommends \
@@ -24,7 +24,7 @@ RUN wget $TOOLCHAIN_URL && \
     tar vxf $(basename $TOOLCHAIN_URL) -C /opt/powerpc64le-toolchain --strip-components=1 && \
     rm -rf  $(basename $TOOLCHAIN_URL)
 
-ENV PATH /opt/powerpc64le-toolchain/bin:$PATH
+ENV PATH $PATH:/opt/powerpc64le-toolchain/bin
 ENV CROSS_COMPILE powerpc64le-linux-
 
 RUN powerpc64le-linux-gcc --version

samples/binaries/hello_world/hello_world.hex

@@ -40,7 +40,7 @@ a64b5a7d14004a39
 60211f0064210000
 618c00003d800000
 658c0000798c07c6
-7d8903a6618c1194
+7d8903a6618c11ac
 480000004e800421
 0000000000000000
 0000000000000000
@@ -516,62 +516,65 @@ e8010010ebc1fff0
 3d20c0003842a000
 6129200060000000
 f922800079290020
-3940001a3d20c000
-7929002061292018
-4e800020f9490000
-0000000000000000
-3c40000100000000
-600000003842a000
-390a0010e9428000
-71290001e9280000
-e86a00084082fff8
-4e8000205463063e
-0000000000000000
-3c40000100000000
-600000003842a000
-390a0010e9428000
-71290008e9280000
-f86a00004082fff8
+3d40001c3d20c000
+614a200061290020
+e929000079290020
+3d40c0007d295392
+794a0020614a2018
+f92a00003929ffff
 000000004e800020
 0000000000000000
 3842a0003c400001
-fbc1fff07c0802a6
-7fc32214fbe1fff8
-f80100107c7f1b78
-7fbff040f821ffd1
-38210030409e000c
-887f00004bffff10
-4bffff993bff0001
-000000004bffffe4
-0000028001000000
-7d4348ae39200000
-409e000c2f8a0000
-4e8000207d234b78
-4bffffe839290001
+e922800060000000
+e948000039090010
+4082fff8714a0001
+5463063ee8690008
+000000004e800020
+0000000000000000
+3842a0003c400001
+e922800060000000
+e948000039090010
+4082fff8714a0008
+4e800020f8690000
+0000000000000000
+3c40000100000000
+7c0802a63842a000
+fbe1fff8fbc1fff0
+7c7f1b787fc32214
+f821ffd1f8010010
+4082000c7c3ff040
+4bfffef438210030
+3bff0001887f0000
+4bffffe44bffff99
+0100000000000000
+7c691b7800000280
+7d4918ae38600000
+4d8200202c0a0000
+4bfffff038630001
 0000000000000000
 3c40000100000000
 7c0802a63842a000
 fbe1fff8fbc1fff0
 3be000007c7e1b78
 f821ffd1f8010010
-4bffffad7fc3f378
-419d000c7fa3f840
-4bfffe8c38210030
+4bffffb17fc3f378
+4181000c7c23f840
+4bfffe7438210030
 3bff00017c7ef8ae
-4bffffdc4bffff15
+4bffffdc4bffff19
 0100000000000000
 3c40000100000280
 7c0802a63842a000
 3fe2fffffbe1fff8
-f80100103bff7240
-4bfffe69f821ffd1
-386372003c62ffff
+f80100103bff7258
+4bfffe51f821ffd1
+386372183c62ffff
 3c62ffff4bffff85
-4bffff7938637238
-5463063e4bfffe8d
-409e00102b83000d
+4bffff7938637250
+5463063e4bfffe91
+408200102803000d
 4bffff617fe3fb78
-4bfffea94bffffe8
+4bfffead4bffffe8
 000000004bffffe0
 0000018001000000
 7266206f6c6c6548
@@ -586,21 +589,21 @@ f80100103bff7240
 0000000000000010
 0141780400527a01
 0000001000010c1b
-fffffdb000000018
-0000000000000040
+fffffd9800000018
+000000000000005c
 0000002c00000010
-00000038fffffddc
+00000038fffffde0
 0000001000000000
-fffffe0000000040
+fffffe0400000040
 0000000000000034
 0000005400000028
-00000050fffffe20
+00000050fffffe24
 9f029e0041094500
 437e4111300e4401
 4106dedf41000e0a
 000000100000000b
-fffffe4400000080
-000000000000002c
+fffffe4800000080
+0000000000000028
 0000009400000028
 00000058fffffe5c
 9f029e0041094500

samples/hello_world/hello_world.c

@@ -9,7 +9,9 @@
 
 static uint64_t potato_uart_base;
 
-#define PROC_FREQ 50000000
+#define SYSCON_BASE 0xc0000000 /* System control regs */
+#define SYS_REG_CLKINFO 0x20
+
 #define UART_FREQ 115200
 #define UART_BASE 0xc0002000
 
@@ -93,9 +95,11 @@ static unsigned long potato_uart_divisor(unsigned long proc_freq, unsigned long
 
 void potato_uart_init(void)
 {
+	uint64_t proc_freq;
 	potato_uart_base = UART_BASE;
 
-	potato_uart_reg_write(POTATO_CONSOLE_CLOCK_DIV, potato_uart_divisor(PROC_FREQ, UART_FREQ));
+	proc_freq = *(volatile uint64_t *)(SYSCON_BASE + SYS_REG_CLKINFO);
+	potato_uart_reg_write(POTATO_CONSOLE_CLOCK_DIV, potato_uart_divisor(proc_freq, UART_FREQ));
 }
 
 int getchar(void)

samples/micropyton

@@ -1 +0,0 @@
-Subproject commit 0bfd55afbe8eb798a806605a735fb3a68dee07a0

src/main/scala/Core.scala

@@ -59,7 +59,7 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int, clockFr
 
   /* Blink an LED, this proves we are out of reset */
   val led = RegInit(0.U(1.W))
-  val (counterValue, counterWrap) = Counter(true.B, 50000000)
+  val (counterValue, counterWrap) = Counter(true.B, clockFreq)
   when (counterWrap) {
     led := ~led
   }