This PR adds support for Polarfire FPGA from Microchip/Microsemi.
The support has also been added to Fusesoc .core file to use the
soon-to-be merged Libero backend.
- Due to a tool incompatibility, Libero does not accept a module
named "pll". Due to this, I've renamed the PLLs to Chiselwatt_pll.
- Fixed formatting for chiselwatt.core file according to YAML lexer.
- Added micropython and helloworls filesets to .core so it's possible to
override the .hex to be used on core generation.
Demo of hello_world and Micropython:
https://twitter.com/carlosedp/status/1362119833324826626
Signed-off-by: Carlos de Paula <me@carlosedp.com>
This adds support for the cheap Colorlight 5A-75B ECP5 based board.
UART RX is on J19, labelled key+ on the silk screen on the back
UART TX is on J1, pin 1.
All the I/Os on this board go through bidirectional level shifters that
appear to be hardwired as outputs. To get an input pin for UART RX, we
use the button I/O which is also routed to connector J19. The downside is
we can't use the button for reset.
One potential issue is that UART TX is 5V but UART RX is 3.3V. To keep
the FPGA happy any attached UART chip needs to output 3.3V, but it also
needs to be 5V tolerant to handle the level shifted input.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
