Break the writeback mux into two chunks so that all units that have RC
instructions mux into an intermediate signal wrRcData. This gets fed into
the compare logic.
Compare instructions are all fed through the Adder, so use the adder
output instead of the writeback mux.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
We need to clean up the nia/fetch handling, but avoid the situation
where we come out of reset right around the time completed goes high.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Lattice Diamond doesn't seem to support SystemVerilog which is a bit
depressing. We only use the syntax in a few places, so fix that up.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
