mirror of
https://github.com/antonblanchard/chiselwatt.git
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101 lines
2.8 KiB
Markdown
101 lines
2.8 KiB
Markdown
# Chiselwatt
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A tiny POWER Open ISA soft processor written in Chisel.
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## Simulation using verilator
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* Chiselwatt uses verilator for simulation. Either install this from your
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distro or build it. Chisel uses sbt (the scala build tool), but unfortunately
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most of the distros package an ancient version. On Fedora you can install an
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upstream version using:
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```
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sudo dnf remove sbt
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sudo curl https://bintray.com/sbt/rpm/rpm | sudo tee /etc/yum.repos.d/bintray-sbt-rpm.repo
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sudo dnf --enablerepo=bintray--sbt-rpm install sbt
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```
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Next build chiselwatt:
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```
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git clone https://github.com/antonblanchard/chiselwatt
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cd chiselwatt
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make
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```
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* A micropython image is included in the repo. To use it, link the memory image into chiselwatt:
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```
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ln -s micropython/firmware.hex insns.hex
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```
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* Now run chiselwatt:
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```
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./chiselwatt
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```
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## Building micropython from scratch
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* You can also build micropython from scratch. If you aren't building natively on a ppc64le box you will need a cross compiler. This may be available on your distro, otherwise grab the the powerpc64le-power8 toolchain from https://toolchains.bootlin.com/. If you are cross compiling, point CROSS_COMPILE at the toolchain. In the example below I installed it in usr/local/powerpc64le-power8--glibc--bleeding-edge-2018.11-1/bin/ and the tools begin with powerpc64-linux-
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```
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git clone https://github.com/micropython/micropython.git
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cd micropython
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cd ports/powerpc
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make CROSS_COMPILE=/usr/local/powerpc64le-power8--glibc--bleeding-edge-2018.11-1/bin/powerpc64le-linux- -j$(nproc)
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cd ../../../
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```
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* Build chiselwatt, import the the micropython image and run it:
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```
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cd chiselwatt
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make
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scripts/bin2hex.py ../micropython/ports/powerpc/build/firmware.bin > insns.hex
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./chiselwatt
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```
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## Synthesis
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Synthesis on FPGAs is supported with yosys/nextpnr. It uses Docker images, so no software other
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than Docker needs to be installed. If you prefer podman you can use that too.
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Edit Makefile to configure your FPGA, JTAG device etc. You will also need to configure the
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amount of block RAM your FPGA supports, by editing `src/main/scala/Core.scala`. Here we are using
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128kB of block RAM:
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```
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chisel3.Driver.execute(Array[String](), () => new Core(64, 128*1024, "insns.hex", 0x0))
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```
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Unfortunately due to an issue in yosys/nextpnr, dual port RAMs are not working. This means we use
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twice as much block RAM as you would expect. This also means Micropython likely won't fit (it needs
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384 kB).
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hello_world should run everywhere, so start with it. Edit `src/main/scala/Core.scala` and set memory
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to `8*1024`. Then copy in the hello_world image:
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```
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cp hello_world/hello_world.hex insns.hex
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```
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To build:
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```
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make chiselwatt.bit
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```
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and to program the FPGA:
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```
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make prog
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```
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## Issues
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Now that it is functional, we have a number of things to add
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- A few instructions
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- Wishbone interconnect
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- Caches
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- Pipelining and bypassing
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