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antonblanchard.chiselwatt/src/main/scala
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Carlos de Paula 9eb5473a61 Improve readme with Fusesoc info and update samples 
Improved build instructions by using Fusesoc as package manager and
multi-target toolchain.
Updated hello_world sample app to fetch clock from SYSCON registers.
Rebuilt all sample applications based on latest version and using SYSCON
Improve Makefile build process for samples.

Signed-off-by: Carlos de Paula <me@carlosedp.com>
2021-02-23 12:08:04 -03:00
..
Adder.scala
Update to Chisel 3.4.0
2020-12-04 18:33:10 +11:00
Control.scala
Update to Chisel 3.4.0
2020-12-04 18:33:10 +11:00
Core.scala
Improve readme with Fusesoc info and update samples
2021-02-23 12:08:04 -03:00
CountZeroes.scala
Update to Chisel 3.4.0
2020-12-04 18:33:10 +11:00
Fetch.scala
Improve memory read timing by removing readData signals
2020-02-05 12:06:17 +11:00
Helpers.scala
Initial import
2020-01-30 05:20:07 +11:00
InstructionHelpers.scala
Initial import
2020-01-30 05:20:07 +11:00
Instructions.scala
Add mcrf
2020-03-02 22:11:27 +11:00
LoadStore.scala
Make clock frequency settable at the top level of Core
2021-02-23 10:46:12 +10:30
LoadStoreByteReverse.scala
Update to Chisel 3.4.0
2020-12-04 18:33:10 +11:00
Logical.scala
Update to Chisel 3.4.0
2020-12-04 18:33:10 +11:00
MemoryBlackBox.scala
Update to Chisel 3.4.0
2020-12-04 18:33:10 +11:00
Nia.scala
Update to Chisel 3.4.0
2020-12-04 18:33:10 +11:00
PopulationCount.scala
Update to Chisel 3.4.0
2020-12-04 18:33:10 +11:00
RegisterFile.scala
Update to Chisel 3.4.0
2020-12-04 18:33:10 +11:00
Rotator.scala
Update to Chisel 3.4.0
2020-12-04 18:33:10 +11:00
SimpleDivider.scala
Update to Chisel 3.4.0
2020-12-04 18:33:10 +11:00
SimpleMultiplier.scala
Update to Chisel 3.4.0
2020-12-04 18:33:10 +11:00
Uart.scala
Update to Chisel 3.4.0
2020-12-04 18:33:10 +11:00