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Reformat simple_ram_behavioural
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard
committed by
Anton Blanchard
Anton Blanchard
parent
fd9e971b2c
commit
1d5e8c2eb4
@@ -8,70 +8,70 @@ use work.wishbone_types.all;
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use work.simple_ram_behavioural_helpers.all;
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entity mw_soc_memory is
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generic (
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RAM_INIT_FILE : string;
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MEMORY_SIZE : integer
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);
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generic (
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RAM_INIT_FILE : string;
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MEMORY_SIZE : integer
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);
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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wishbone_in : in wishbone_master_out;
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wishbone_out : out wishbone_slave_out
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);
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wishbone_in : in wishbone_master_out;
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wishbone_out : out wishbone_slave_out
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);
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end mw_soc_memory;
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architecture behave of mw_soc_memory is
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type wishbone_state_t is (IDLE, ACK);
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type wishbone_state_t is (IDLE, ACK);
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signal state : wishbone_state_t := IDLE;
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signal ret_ack : std_ulogic := '0';
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signal identifier : integer := behavioural_initialize(filename => RAM_INIT_FILE, size => MEMORY_SIZE);
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signal reload : integer := 0;
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signal state : wishbone_state_t := IDLE;
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signal ret_ack : std_ulogic := '0';
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signal identifier : integer := behavioural_initialize(filename => RAM_INIT_FILE, size => MEMORY_SIZE);
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signal reload : integer := 0;
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begin
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wishbone_process: process(clk)
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variable ret_dat: std_ulogic_vector(63 downto 0) := (others => '0');
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begin
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wishbone_out.ack <= ret_ack and wishbone_in.cyc and wishbone_in.stb;
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wishbone_out.dat <= ret_dat;
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wishbone_process: process(clk)
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variable ret_dat: std_ulogic_vector(63 downto 0) := (others => '0');
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begin
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wishbone_out.ack <= ret_ack and wishbone_in.cyc and wishbone_in.stb;
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wishbone_out.dat <= ret_dat;
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if rising_edge(clk) then
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if rst = '1' then
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state <= IDLE;
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ret_ack <= '0';
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else
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ret_dat := x"FFFFFFFFFFFFFFFF";
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if rising_edge(clk) then
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if rst = '1' then
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state <= IDLE;
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ret_ack <= '0';
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else
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ret_dat := x"FFFFFFFFFFFFFFFF";
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-- Active
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if wishbone_in.cyc = '1' then
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case state is
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when IDLE =>
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if wishbone_in.stb = '1' then
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-- write
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if wishbone_in.we = '1' then
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assert not(is_x(wishbone_in.dat)) and not(is_x(wishbone_in.adr)) severity failure;
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report "RAM writing " & to_hstring(wishbone_in.dat) & " to " & to_hstring(wishbone_in.adr);
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behavioural_write(wishbone_in.dat, wishbone_in.adr, to_integer(unsigned(wishbone_in.sel)), identifier);
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reload <= reload + 1;
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ret_ack <= '1';
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state <= ACK;
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else
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behavioural_read(ret_dat, wishbone_in.adr, to_integer(unsigned(wishbone_in.sel)), identifier, reload);
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report "RAM reading from " & to_hstring(wishbone_in.adr) & " returns " & to_hstring(ret_dat);
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ret_ack <= '1';
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state <= ACK;
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end if;
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end if;
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when ACK =>
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ret_ack <= '0';
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state <= IDLE;
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end case;
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else
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ret_ack <= '0';
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state <= IDLE;
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end if;
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end if;
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end if;
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end process;
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-- Active
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if wishbone_in.cyc = '1' then
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case state is
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when IDLE =>
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if wishbone_in.stb = '1' then
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-- write
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if wishbone_in.we = '1' then
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assert not(is_x(wishbone_in.dat)) and not(is_x(wishbone_in.adr)) severity failure;
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report "RAM writing " & to_hstring(wishbone_in.dat) & " to " & to_hstring(wishbone_in.adr);
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behavioural_write(wishbone_in.dat, wishbone_in.adr, to_integer(unsigned(wishbone_in.sel)), identifier);
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reload <= reload + 1;
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ret_ack <= '1';
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state <= ACK;
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else
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behavioural_read(ret_dat, wishbone_in.adr, to_integer(unsigned(wishbone_in.sel)), identifier, reload);
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report "RAM reading from " & to_hstring(wishbone_in.adr) & " returns " & to_hstring(ret_dat);
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ret_ack <= '1';
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state <= ACK;
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end if;
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end if;
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when ACK =>
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ret_ack <= '0';
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state <= IDLE;
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end case;
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else
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ret_ack <= '0';
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state <= IDLE;
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end if;
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end if;
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end if;
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end process;
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end behave;
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@@ -2,29 +2,29 @@ library ieee;
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use ieee.std_logic_1164.all;
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package simple_ram_behavioural_helpers is
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function behavioural_initialize (filename: String; size: integer) return integer;
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attribute foreign of behavioural_initialize : function is "VHPIDIRECT behavioural_initialize";
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function behavioural_initialize (filename: String; size: integer) return integer;
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attribute foreign of behavioural_initialize : function is "VHPIDIRECT behavioural_initialize";
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procedure behavioural_read (val: out std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer; reload: integer);
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attribute foreign of behavioural_read : procedure is "VHPIDIRECT behavioural_read";
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procedure behavioural_read (val: out std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer; reload: integer);
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attribute foreign of behavioural_read : procedure is "VHPIDIRECT behavioural_read";
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procedure behavioural_write (val: std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer);
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attribute foreign of behavioural_write : procedure is "VHPIDIRECT behavioural_write";
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procedure behavioural_write (val: std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer);
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attribute foreign of behavioural_write : procedure is "VHPIDIRECT behavioural_write";
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end simple_ram_behavioural_helpers;
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package body simple_ram_behavioural_helpers is
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function behavioural_initialize (filename: String; size: integer) return integer is
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begin
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assert false report "VHPI" severity failure;
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end behavioural_initialize;
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function behavioural_initialize (filename: String; size: integer) return integer is
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begin
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assert false report "VHPI" severity failure;
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end behavioural_initialize;
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procedure behavioural_read (val: out std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer; reload: integer) is
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begin
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assert false report "VHPI" severity failure;
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end behavioural_read;
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procedure behavioural_read (val: out std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer; reload: integer) is
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begin
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assert false report "VHPI" severity failure;
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end behavioural_read;
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procedure behavioural_write (val: std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer) is
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begin
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assert false report "VHPI" severity failure;
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end behavioural_write;
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procedure behavioural_write (val: std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer) is
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begin
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assert false report "VHPI" severity failure;
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end behavioural_write;
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end simple_ram_behavioural_helpers;
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@@ -9,225 +9,233 @@ entity simple_ram_behavioural_tb is
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end simple_ram_behavioural_tb;
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architecture behave of simple_ram_behavioural_tb is
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signal clk : std_ulogic;
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signal rst : std_ulogic := '1';
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signal clk : std_ulogic;
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signal rst : std_ulogic := '1';
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constant clk_period : time := 10 ns;
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constant clk_period : time := 10 ns;
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signal w_in : wishbone_slave_out;
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signal w_out : wishbone_master_out;
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signal w_in : wishbone_slave_out;
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signal w_out : wishbone_master_out;
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begin
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simple_ram_0: entity work.mw_soc_memory
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generic map ( RAM_INIT_FILE => "simple_ram_behavioural_tb.bin", MEMORY_SIZE => 16 )
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port map (clk => clk, rst => rst, wishbone_out => w_in, wishbone_in => w_out);
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simple_ram_0: entity work.mw_soc_memory
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generic map (
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RAM_INIT_FILE => "simple_ram_behavioural_tb.bin",
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MEMORY_SIZE => 16
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)
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port map (
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clk => clk,
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rst => rst,
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wishbone_out => w_in,
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wishbone_in => w_out
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);
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clock: process
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begin
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clk <= '1';
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wait for clk_period / 2;
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clk <= '0';
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wait for clk_period / 2;
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end process clock;
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clock: process
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begin
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clk <= '1';
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wait for clk_period / 2;
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clk <= '0';
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wait for clk_period / 2;
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end process clock;
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stim: process
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begin
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w_out.adr <= (others => '0');
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w_out.dat <= (others => '0');
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w_out.cyc <= '0';
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w_out.stb <= '0';
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w_out.sel <= (others => '0');
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w_out.we <= '0';
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stim: process
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begin
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w_out.adr <= (others => '0');
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w_out.dat <= (others => '0');
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w_out.cyc <= '0';
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w_out.stb <= '0';
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w_out.sel <= (others => '0');
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w_out.we <= '0';
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wait for clk_period;
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rst <= '0';
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wait for clk_period;
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rst <= '0';
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wait for clk_period;
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wait for clk_period;
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w_out.cyc <= '1';
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w_out.cyc <= '1';
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-- test various read lengths and alignments
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w_out.stb <= '1';
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w_out.sel <= "00000001";
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w_out.adr <= x"0000000000000000";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(7 downto 0) = x"00" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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-- test various read lengths and alignments
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w_out.stb <= '1';
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w_out.sel <= "00000001";
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w_out.adr <= x"0000000000000000";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(7 downto 0) = x"00" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00000001";
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w_out.adr <= x"0000000000000001";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(7 downto 0) = x"01" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00000001";
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w_out.adr <= x"0000000000000001";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(7 downto 0) = x"01" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00000001";
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w_out.adr <= x"0000000000000007";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(7 downto 0) = x"07" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00000001";
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w_out.adr <= x"0000000000000007";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(7 downto 0) = x"07" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00000011";
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w_out.adr <= x"0000000000000000";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(15 downto 0) = x"0100" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00000011";
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w_out.adr <= x"0000000000000000";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(15 downto 0) = x"0100" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00000011";
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w_out.adr <= x"0000000000000001";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(15 downto 0) = x"0201" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00000011";
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w_out.adr <= x"0000000000000001";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(15 downto 0) = x"0201" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00000011";
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w_out.adr <= x"0000000000000007";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(15 downto 0) = x"0807" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00000011";
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w_out.adr <= x"0000000000000007";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(15 downto 0) = x"0807" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00001111";
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w_out.adr <= x"0000000000000000";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(31 downto 0) = x"03020100" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00001111";
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w_out.adr <= x"0000000000000000";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(31 downto 0) = x"03020100" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00001111";
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w_out.adr <= x"0000000000000001";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(31 downto 0) = x"04030201" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00001111";
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w_out.adr <= x"0000000000000001";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(31 downto 0) = x"04030201" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
|
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w_out.sel <= "00001111";
|
||||
w_out.adr <= x"0000000000000007";
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(31 downto 0) = x"0A090807" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "00001111";
|
||||
w_out.adr <= x"0000000000000007";
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(31 downto 0) = x"0A090807" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= x"0000000000000000";
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(63 downto 0) = x"0706050403020100" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= x"0000000000000000";
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(63 downto 0) = x"0706050403020100" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= x"0000000000000001";
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(63 downto 0) = x"0807060504030201" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= x"0000000000000001";
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(63 downto 0) = x"0807060504030201" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= x"0000000000000007";
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(63 downto 0) = x"0E0D0C0B0A090807" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= x"0000000000000007";
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(63 downto 0) = x"0E0D0C0B0A090807" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
-- test various write lengths and alignments
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "00000001";
|
||||
w_out.adr <= x"0000000000000000";
|
||||
w_out.we <= '1';
|
||||
w_out.dat(7 downto 0) <= x"0F";
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
-- test various write lengths and alignments
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "00000001";
|
||||
w_out.adr <= x"0000000000000000";
|
||||
w_out.we <= '1';
|
||||
w_out.dat(7 downto 0) <= x"0F";
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "00000001";
|
||||
w_out.adr <= x"0000000000000000";
|
||||
w_out.we <= '0';
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(7 downto 0) = x"0F" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "00000001";
|
||||
w_out.adr <= x"0000000000000000";
|
||||
w_out.we <= '0';
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat(7 downto 0) = x"0F" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= x"0000000000000007";
|
||||
w_out.we <= '1';
|
||||
w_out.dat <= x"BADC0FFEBADC0FFE";
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= x"0000000000000007";
|
||||
w_out.we <= '1';
|
||||
w_out.dat <= x"BADC0FFEBADC0FFE";
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= x"0000000000000007";
|
||||
w_out.we <= '0';
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat = x"BADC0FFEBADC0FFE" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
w_out.stb <= '1';
|
||||
w_out.sel <= "11111111";
|
||||
w_out.adr <= x"0000000000000007";
|
||||
w_out.we <= '0';
|
||||
assert w_in.ack = '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '1';
|
||||
assert w_in.dat = x"BADC0FFEBADC0FFE" report to_hstring(w_in.dat);
|
||||
w_out.stb <= '0';
|
||||
wait for clk_period;
|
||||
assert w_in.ack = '0';
|
||||
|
||||
assert false report "end of test" severity failure;
|
||||
wait;
|
||||
end process;
|
||||
assert false report "end of test" severity failure;
|
||||
wait;
|
||||
end process;
|
||||
end behave;
|
||||
|
||||
Reference in New Issue
Block a user