github.com/antonblanchard.microwatt
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28debecf1ab6a1966b0fde6b810a327c36206812
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3 Commits

Author SHA1 Message Date
Anton Blanchard
28debecf1a Add ASIC target 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2022-08-22 14:43:21 +10:00
Anton Blanchard
01f8ad55ef Move register stage from after RAM to before RAM 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2022-08-22 14:43:21 +10:00
Anton Blanchard
52f2462232 Add arrays for ASIC flow 
Add VHDL wrappers and verilog behaviourals for the cache_ram,
register_file and main_bram arrays.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2022-08-22 14:43:21 +10:00