9 Commits

Author	SHA1	Message	Date
Anton Blanchard	6d85920068	execute1 no longer needs sim_console ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	2019-09-16 11:18:53 +10:00
Michael Neuling	1e1b799382	Remove FIXME comment ... This was mistakenly left behind in 4d5abfb430 ("Remove dynamic ranges from code") Signed-off-by: Michael Neuling <mikey@neuling.org>	2019-09-11 16:51:02 +10:00
Anton Blanchard	a2df2a10a2	Remove sim console ... We can force all existing code to use the UART console by passing 0 in bit zero of the sim config register. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	2019-09-11 13:23:45 +10:00
Anton Blanchard	a8f8c54b77	Move debug execute output into decode2 ... This covers all units, and we avoid double printing. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	2019-09-11 13:23:45 +10:00
Anton Blanchard	92a7152370	Rework pipeline, add stall and flush signals ... This adds stall and flush signals to the pipeline. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	2019-09-11 13:23:45 +10:00
Michael Neuling	4d5abfb430	Remove dynamic ranges from code ... Some VHDL compilers like verific [1] don't like these, so let's remove them. Lots of random code changes, but passes make check. Also add basic script to run verific and generate verilog. 1. https://www.verific.com/ Signed-off-by: Michael Neuling <mikey@neuling.org>	2019-08-30 16:13:48 +10:00
Anton Blanchard	0fd18c2455	Add srd and srw ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	2019-08-28 14:50:37 +10:00
Anton Blanchard	73daacbcd4	Add sim only divw ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	2019-08-28 14:07:29 +10:00
Anton Blanchard	5a29cb4699	Initial import of microwatt ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	2019-08-22 16:46:13 +10:00