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antonblanchard.microwatt/fpga
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Benjamin Herrenschmidt e638c3e8ae fpga/bram: Generate stall signal 
This doesn't yet pipeline the block RAM, just generate a valid stall
signal so it's compatible with a pipelined master

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-10-30 13:18:58 +11:00
..
arty_a7.xdc
fpga: Arty A7's don't need multiple filesets
2019-09-30 12:56:47 +10:00
clk_gen_bypass.vhd
Fix clk_gen_bypass
2019-10-13 14:41:53 +11:00
clk_gen_mcmm.vhd
Improve PLL/MMCM clocks configuration
2019-09-30 13:57:36 +10:00
clk_gen_plle2.vhd
Improve PLL/MMCM clocks configuration
2019-09-30 13:57:36 +10:00
cmod_a7-35.xdc
Cmod A7-35 support
2019-09-08 16:36:50 +10:00
firmware.hex
Add a few more FPGA related files
2019-08-23 16:23:53 +10:00
hello_world.hex
Rebuild hello world assuming a 50MHz clock
2019-08-26 22:09:28 +10:00
LICENSE
Initial import of microwatt
2019-08-22 16:46:13 +10:00
mw_soc_memory.vhdl
fpga/bram: Generate stall signal
2019-10-30 13:18:58 +11:00
nexys_a7.xdc
Merge pull request #20 from antonblanchard/reset-rework2
2019-09-08 16:34:10 +10:00
nexys-video.xdc
Rename a few reset signals
2019-09-07 21:33:50 +10:00
pp_fifo.vhd
fifo: Reformat
2019-10-13 12:57:23 +11:00
pp_soc_uart.vhd
pp_uart: reformat
2019-10-30 13:18:58 +11:00
pp_utilities.vhd
Initial import of microwatt
2019-08-22 16:46:13 +10:00
soc_reset_tb.vhdl
Rework SOC reset
2019-09-08 07:40:19 +10:00
soc_reset.vhdl
Rework SOC reset
2019-09-08 07:40:19 +10:00
toplevel.vhdl
Improve PLL/MMCM clocks configuration
2019-09-30 13:57:36 +10:00