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antonblanchard.microwatt/fpga
History
Paul Mackerras bf55efec6d Arty A7: Add an option to select the number of CPU cores 
Timing is currently not very good with 2 cores on the Arty A7-100.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2025-01-18 10:05:41 +11:00
..
acorn-cle-215.xdc
acorn: Add support for the Acorn CLE 215+
2020-08-07 15:42:07 +10:00
antmicro_artix_dc_scm.xdc
antmicro-artix-dc-scm: Add Ethernet pins
2022-08-31 18:36:26 +09:30
arty_a7.xdc
arty a7: Fix build error with Vivado (#429)
2024-04-10 19:09:02 +10:00
clk_gen_bypass.vhd
…
clk_gen_ecp5.vhd
ECP5: Adjust PLL constants so the PLL lock indication works
2021-10-16 20:14:12 +11:00
clk_gen_mcmm.vhd
Fix some whitespace issues
2021-08-09 11:57:00 +10:00
clk_gen_plle2.vhd
fpga/clk_gen_plle2: Add support for 50Mhz->100Mhz
2021-09-25 18:18:32 +10:00
cmod_a7-35.xdc
Remove -add from xdc files
2021-08-09 13:30:26 +10:00
firmware.hex
…
fpga-random.vhdl
…
fpga-random.xdc
…
genesys2.xdc
Remove -waveform from xdc files
2021-08-09 13:30:26 +10:00
hello_world.hex
…
LICENSE
…
main_bram.vhdl
Rename 'do' signal to avoid verilator System Verilog warning
2021-08-13 13:52:51 +10:00
nexys_a7.xdc
Remove -add from xdc files
2021-08-09 13:30:26 +10:00
nexys-video.xdc
litesdcard: Add Nexys Video support
2021-08-10 14:08:22 +10:00
pp_fifo.vhd
…
pp_soc_uart.vhd
…
pp_utilities.vhd
…
soc_reset_tb.vhdl
…
soc_reset.vhdl
…
top-acorn-cle-215.vhdl
Move alt_reset to syscon
2022-10-31 14:41:15 +08:00
top-antmicro-artix-dc-scm.vhdl
Move alt_reset to syscon
2022-10-31 14:41:15 +08:00
top-arty.vhdl
Arty A7: Add an option to select the number of CPU cores
2025-01-18 10:05:41 +11:00
top-ecpix5.vhdl
ECPIX-5: Add liteeth support
2024-04-09 14:22:01 +10:00
top-generic.vhdl
Remove option for "short" 16x16 bit multiplier
2022-08-10 11:27:45 +10:00
top-genesys2.vhdl
Move alt_reset to syscon
2022-10-31 14:41:15 +08:00
top-nexys-video.vhdl
liteeth: Regenerate from current upstream litex
2024-04-06 19:14:50 +11:00
top-orangecrab0.2.vhdl
Move alt_reset to syscon
2022-10-31 14:41:15 +08:00
top-wukong-v2.vhdl
liteeth: Regenerate from current upstream litex
2024-04-06 19:14:50 +11:00
wukong-v2.xdc
Add support for QMTech Wukong v2 board
2021-09-25 18:18:32 +10:00