beeanyew
b5bf4fb3fd
Actually fix Chip fastpath
2021-08-12 08:18:41 +02:00
beeanyew
88c8b9d47c
Some stability improvements for Chip fastpath?
2021-08-10 15:41:00 +02:00
beeanyew
f12b0f0488
Make Chip RAM fastpath optional
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Use `make ACFLAGS=-DCHIP_FASTPATH` to compile it into your build.
2021-08-01 19:02:55 +02:00
beeanyew
7a10901dc6
Experimental Chip speed hax
2021-08-01 09:39:27 +02:00
beeanyew
6e1a95011d
Fix the stupid. Don't do things on four hours of sleep.
2021-07-31 23:10:38 +02:00
beeanyew
bfd906f216
Fix the Musashi write translation cache
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Many thanks to Sesse for noticing this hiccup. Probably requires a `make clean` and then `make`.
2021-07-31 22:49:22 +02:00
beeanyew
208ba3d79d
Get rid of Musashi separate writes
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The separate writes functionality of Musashi was severely getting in the way of any kind of caching of bus longwords, and I found that the negatvie performance impact of disabling separate writes could be negated by creatively applying the address translation cache to the FC reads/writes instead.
This commit requires a `make clean` before rebuilding the emulator with `make`.
2021-06-28 15:08:28 +02:00
beeanyew
9b1031c859
Fix Musashi compilation with prefetch emulation disabled
2021-06-27 19:20:22 +02:00
beeanyew
75c73650a6
Fix Musashi compilation with MMU emulation enabled
2021-06-24 09:34:29 +02:00
Rune Holm
0c763fca70
introducing CPU state parameter 5 - now switched most register state over
2021-06-20 21:42:03 +01:00
Rune Holm
514f1d4e24
introducing CPU state parameter 4
2021-06-20 21:41:55 +01:00
Rune Holm
d06400230f
introducing CPU state parameter 3
2021-06-20 21:35:37 +01:00
Rune Holm
6d74804193
introducing CPU state paramter 2
2021-06-20 21:54:08 +02:00
Rune Holm
14636790c6
introducing CPU state parameter
2021-06-20 21:54:05 +02:00
Rune Holm
18cba7ddc6
step 1: add a state parameter to all opcode functions
2021-06-20 21:50:15 +02:00
Rune Holm
a2b0521dbd
move address translation cache fields from global variables to the m68k struct, as
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this way we can pass around one pointer and access them all in the future.
This happens to win 5-10% performance, because now the code generator can generate a single
global variable pointer to get to all of the translation cache/range fields at once.
2021-06-18 22:01:22 +01:00
Rune Holm
b91e0e809d
optimise away an unnecessary subtract on the instruction fetch fast path
2021-06-18 22:01:20 +01:00
beeanyew
62d18f9f13
Merge branch 'wip-crap' into main
2021-06-11 21:38:36 +02:00
Rune Holm
fe3b4bb032
pull the PC masking into the code translation cache, so that we only need to mask the PC on our slow path. Gives us another 5-10% speedup.
2021-06-11 19:34:03 +01:00
Rune Holm
3203ac8590
Created address translation fast path for code reads, separated slow path into separate function so the fast path is more likely to be inlined. 10-20% performance improvement
2021-06-11 18:37:57 +01:00
beeanyew
d882c8da74
Fix Musashi complation with various m68conf options
2021-05-07 00:46:19 +02:00
beeanyew
83fa34909f
Fix up Musashi performance with prefetch enabled
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Mapped memory ranges should always be given preference, since they can't actually cause a bus error or affect any read/write operations over the 68k bus.
2021-04-16 10:47:25 +02:00
shanshe
b2121be23f
Bus Error and 68k OPs update (to latest MAME)
2021-04-13 18:31:06 +02:00
shanshe
e48448eff9
MMU and InstructionCache update (MAME's latest code)
2021-04-13 10:32:30 +02:00
shanshe
6c9276f882
FPU update as latest MAME
2021-04-13 10:00:48 +02:00
beeanyew
1f804c7e36
[WIP] IRQ experiments, revert Musashi speed hax for now
2021-03-08 15:53:23 +01:00
beeanyew
60acb37185
Certified Musashi speed hax
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Probably requires a make clean due to things being in header files.
2021-02-18 05:29:59 +01:00
beeanyew
2e76e75128
Some Musashi mapping and RTG fixes/debug
2021-01-06 13:13:05 +01:00
beeanyew
4ee88c2266
Fix all the colors, fix some other stuff.
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Workbench still doesn't work.
2021-01-06 04:56:33 +01:00
beeanyew
2e157e0665
Fix the stupid
2020-12-31 17:21:06 +01:00
beeanyew
2eb8474c92
Plug some read/write mappings directly into Musashi
2020-12-31 12:15:42 +01:00
Claude
e2f86a9c1a
first commit
2020-10-31 09:26:56 +01:00
