2. Selected new type of MSRs (F: Fuse Controlled) which availability is controlled by CPU core's fuse configuration (64-bit OTP data programmed at manufacturing stage)
3. For each MSR, the fuse index field from its descriptor is printed in the MSR decription list. The field is only used for MSRs of type F
2. Secure Enclave (SGX) SVN key generation is found
3. A Python module is implemented for the disassembler
4. Many other microarchitectural data are found and added