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https://github.com/kalymos/PsNee.git
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mor test
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kalymos
@@ -296,3 +296,94 @@
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#endif
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// #ifdef BIOS_PATCH
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// // Shared variables between ISR and main loop
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// volatile uint8_t pulse_counter = 0;
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// volatile uint8_t patch_done = 0;
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// // --- Utility function for a CPU cycle delay (NOP) ---
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// static inline void delay_cycles(uint8_t cycles) {
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// while(cycles--) {
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// asm volatile("nop");
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// }
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// }
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// // --- MAIN INTERRUPT SERVICE ROUTINE (ADDRESS AX) ---
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// ISR(PIN_AX_INTERRUPT_VECTOR) {
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// if (--pulse_counter == 0) {
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// // --- PHASE 4: Precision Bit Alignment ---
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// delay_cycles(BIT_OFFSET_CYCLES);
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// // --- PHASE 5: Data Bus Overdrive (Patch applied on DX) ---
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// #ifdef INTERRUPT_RISING_HIGH_PATCH
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// PIN_DX_SET; // Pre-set HIGH if needed for this variant
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// #endif
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// PIN_DX_OUTPUT; // Take control of the data bus
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// delay_cycles(OVERRIDE_CYCLES);
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// #ifdef INTERRUPT_RISING_HIGH_PATCH
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// PIN_DX_CLEAR; // Release HIGH state
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// #endif
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// PIN_DX_INPUT; // Immediately release the data bus
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// PIN_AX_INTERRUPT_DISABLE;
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// patch_done = 1; // Signal completion of stage 1
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// }
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// }
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// // --- SECONDARY ISR (ADDRESS AY, HIGH_PATCH variant) ---
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// #ifdef INTERRUPT_RISING_HIGH_PATCH
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// ISR(PIN_AY_INTERRUPT_VECTOR) {
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// if (--pulse_counter == 0) {
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// delay_cycles(BIT_OFFSET_2_CYCLES);
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// PIN_DX_OUTPUT;
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// delay_cycles(OVERRIDE_2_CYCLES);
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// PIN_DX_INPUT;
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// PIN_AY_INTERRUPT_DISABLE;
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// patch_done = 2; // Signal completion of stage 2
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// }
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// }
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// #endif
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// // --- BIOS Patching Main Function ---
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// void Bios_Patching(void) {
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// // --- PHASE 1: Signal Stabilization & Alignment (AX) ---
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// if (PIN_AX_READ != 0) { // Case: Power-on, line is high
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// while (PIN_AX_READ != 0); // Wait for falling edge
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// while (PIN_AX_READ == 0); // Wait for next rising edge to sync
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// } else { // Case: Reset, line is low
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// while (PIN_AX_READ == 0); // Wait for first rising edge
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// }
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// // --- PHASE 2: Reaching the Target Memory Window ---
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// _delay_ms(BOOT_OFFSET_MS);
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// // --- Prepare pulse counter and patch status flag ---
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// pulse_counter = PULSE_COUNT;
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// patch_done = 0;
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// // --- Dynamic interrupt configuration ---
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// #if defined(INTERRUPT_RISING) || defined(INTERRUPT_RISING_HIGH_PATCH)
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// PIN_AX_INTERRUPT_RISING;
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// #elif defined(INTERRUPT_FALLING)
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// PIN_AX_INTERRUPT_FALLING;
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// #endif
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// PIN_AX_INTERRUPT_ENABLE;
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// while (patch_done != 1); // Wait until stage 1 is completed
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// // --- Optional secondary patch phase for HIGH_PATCH ---
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// #ifdef INTERRUPT_RISING_HIGH_PATCH
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// while (PIN_AY_READ != 0); // Ensure AY line is low before arming
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// _delay_ms(FOLLOWUP_OFFSET_MS);
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// pulse_counter = PULSE_COUNT_2; // Reload counter for AY pulses
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// PIN_AY_INTERRUPT_RISING;
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// PIN_AY_INTERRUPT_ENABLE;
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// while (patch_done != 2); // Wait until stage 2 is completed
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// #endif
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// }
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// #endif
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@@ -260,10 +260,12 @@
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#include <util/delay.h>
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// Global interrupt control settings
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#define GLOBAL_INTERRUPT_ENABLE SREG |= (1 << 7) // Set the I-bit (bit 7) in the Status Register to enable global interrupts
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#define GLOBAL_INTERRUPT_DISABLE SREG &= ~(1 << 7) // Clear the I-bit (bit 7) in the Status Register to disable global interrupts
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#define GLOBAL_INTERRUPT_ENABLE sei()
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#define GLOBAL_INTERRUPT_DISABLE cli()
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// #define GLOBAL_INTERRUPT_ENABLE SREG |= (1 << 7) // Set the I-bit (bit 7) in the Status Register to enable global interrupts
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// #define GLOBAL_INTERRUPT_DISABLE SREG &= ~(1 << 7) // Clear the I-bit (bit 7) in the Status Register to disable global interrupts
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// Main pin configuration for input and output
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// Main pin configuration
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// Define the main pins as inputs
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#define PIN_DATA_INPUT DDRB &= ~(1 << DDB0) // Set DDRB register to configure PINB0 as input
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180
PSNee/settings.h
180
PSNee/settings.h
@@ -115,6 +115,186 @@
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#define OVERRIDE_2 0.15
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#endif
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// // -------- SCPH 102 --------
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// #ifdef SCPH_102
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// #define BIOS_PATCH_2
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// #define INTERRUPT_RISING
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// #ifdef F_CPU_8MHZ
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// #define BOOT_OFFSET_MS 84
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// #define PULSE_COUNT 48
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// #define BIT_OFFSET_CYCLES 26 // 3.25us / 0.125us ≈ 26 cycles
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// #define OVERRIDE_CYCLES 2 // 0.2us / 0.125us ≈ 2 cycles
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// #elif defined(F_CPU_16MHZ)
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// #define BOOT_OFFSET_MS 84
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// #define PULSE_COUNT 48
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// #define BIT_OFFSET_CYCLES 52 // 3.25 / 0.0625 ≈ 52 cycles
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// #define OVERRIDE_CYCLES 3 // 0.2 / 0.0625 ≈ 3 cycles
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// #endif
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// #endif
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// // -------- SCPH 100 --------
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// #ifdef SCPH_100
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// #define BIOS_PATCH
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// #define INTERRUPT_RISING
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// #ifdef F_CPU_8MHZ
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// #define BOOT_OFFSET_MS 84
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// #define PULSE_COUNT 48
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// #define BIT_OFFSET_CYCLES 22 // 2.75 / 0.125 ≈ 22 cycles
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// #define OVERRIDE_CYCLES 2 // 0.2 / 0.125 ≈ 2 cycles
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// #elif defined(F_CPU_16MHZ)
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// #define BOOT_OFFSET_MS 84
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// #define PULSE_COUNT 48
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// #define BIT_OFFSET_CYCLES 44 // 2.75 / 0.0625 ≈ 44 cycles
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// #define OVERRIDE_CYCLES 3 // 0.2 / 0.0625 ≈ 3 cycles
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// #endif
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// #endif
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// // -------- SCPH 7500 / 9000 --------
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// #ifdef SCPH_7500_9000
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// #define BIOS_PATCH
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// #define INTERRUPT_RISING
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// #ifdef F_CPU_8MHZ
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// #define BOOT_OFFSET_MS 75
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// #define PULSE_COUNT 16
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// #define BIT_OFFSET_CYCLES 22 // 2.8 / 0.125 ≈ 22 cycles
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// #define OVERRIDE_CYCLES 2 // 0.2 / 0.125 ≈ 2 cycles
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// #elif defined(F_CPU_16MHZ)
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// #define BOOT_OFFSET_MS 75
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// #define PULSE_COUNT 16
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// #define BIT_OFFSET_CYCLES 45 // 2.8 / 0.0625 ≈ 45 cycles
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// #define OVERRIDE_CYCLES 3 // 0.2 / 0.0625 ≈ 3 cycles
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// #endif
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// #endif
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// // -------- SCPH 7000 --------
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// #ifdef SCPH_7000
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// #define BIOS_PATCH
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// #define INTERRUPT_RISING
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// #ifdef F_CPU_8MHZ
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// #define BOOT_OFFSET_MS 75
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// #define PULSE_COUNT 16
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// #define BIT_OFFSET_CYCLES 22
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// #define OVERRIDE_CYCLES 2
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// #elif defined(F_CPU_16MHZ)
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// #define BOOT_OFFSET_MS 75
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// #define PULSE_COUNT 16
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// #define BIT_OFFSET_CYCLES 45
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// #define OVERRIDE_CYCLES 3
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// #endif
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// #endif
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// // -------- SCPH 5500 --------
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// #ifdef SCPH_5500
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// #define BIOS_PATCH
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// #define INTERRUPT_FALLING
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// #ifdef F_CPU_8MHZ
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// #define BOOT_OFFSET_MS 76
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// #define PULSE_COUNT 21
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// #define BIT_OFFSET_CYCLES 22
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// #define OVERRIDE_CYCLES 2
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// #elif defined(F_CPU_16MHZ)
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// #define BOOT_OFFSET_MS 76
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// #define PULSE_COUNT 21
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// #define BIT_OFFSET_CYCLES 45
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// #define OVERRIDE_CYCLES 3
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// #endif
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// #endif
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// // -------- SCPH 5000 --------
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// #ifdef SCPH_5000
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// #define BIOS_PATCH
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// #define INTERRUPT_FALLING
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// #ifdef F_CPU_8MHZ
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// #define BOOT_OFFSET_MS 75
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// #define PULSE_COUNT 21
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// #define BIT_OFFSET_CYCLES 22
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// #define OVERRIDE_CYCLES 1
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// #elif defined(F_CPU_16MHZ)
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// #define BOOT_OFFSET_MS 75
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// #define PULSE_COUNT 21
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// #define BIT_OFFSET_CYCLES 45
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// #define OVERRIDE_CYCLES 2
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// #endif
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// #endif
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// // -------- SCPH 3500 --------
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// #ifdef SCPH_3500
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// #define BIOS_PATCH
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// #define INTERRUPT_FALLING
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// #ifdef F_CPU_8MHZ
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// #define BOOT_OFFSET_MS 75
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// #define PULSE_COUNT 21
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// #define BIT_OFFSET_CYCLES 22
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// #define OVERRIDE_CYCLES 2
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// #elif defined(F_CPU_16MHZ)
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// #define BOOT_OFFSET_MS 75
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// #define PULSE_COUNT 21
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// #define BIT_OFFSET_CYCLES 44
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// #define OVERRIDE_CYCLES 3
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// #endif
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// #endif
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// // -------- SCPH 3000 --------
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// #ifdef SCPH_3000
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// #define BIOS_PATCH
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// #define INTERRUPT_RISING_HIGH_PATCH
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// #define HIGH_PATCH
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// #ifdef F_CPU_8MHZ
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// #define BOOT_OFFSET_MS 83
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// #define PULSE_COUNT 60
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// #define BIT_OFFSET_CYCLES 22
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// #define OVERRIDE_CYCLES 1
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// #define FOLLOWUP_OFFSET_MS 253
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// #define PULSE_COUNT_2 43
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// #define BIT_OFFSET_2_CYCLES 23
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// #define OVERRIDE_2_CYCLES 1
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// #elif defined(F_CPU_16MHZ)
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// #define BOOT_OFFSET_MS 83
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// #define PULSE_COUNT 60
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// #define BIT_OFFSET_CYCLES 43
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// #define OVERRIDE_CYCLES 2
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// #define FOLLOWUP_OFFSET_MS 253
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// #define PULSE_COUNT_2 43
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// #define BIT_OFFSET_2_CYCLES 46
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// #define OVERRIDE_2_CYCLES 2
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// #endif
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// #endif
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// // -------- SCPH 1000 --------
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// #ifdef SCPH_1000
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// #define BIOS_PATCH
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// #define INTERRUPT_RISING_HIGH_PATCH
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// #define HIGH_PATCH
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// #ifdef F_CPU_8MHZ
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// #define BOOT_OFFSET_MS 83
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// #define PULSE_COUNT 92
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// #define BIT_OFFSET_CYCLES 21
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// #define OVERRIDE_CYCLES 1
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// #define FOLLOWUP_OFFSET_MS 273
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// #define PULSE_COUNT_2 71
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// #define BIT_OFFSET_2_CYCLES 23
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// #define OVERRIDE_2_CYCLES 1
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// #elif defined(F_CPU_16MHZ)
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// #define BOOT_OFFSET_MS 83
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// #define PULSE_COUNT 92
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// #define BIT_OFFSET_CYCLES 42
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// #define OVERRIDE_CYCLES 2
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// #define FOLLOWUP_OFFSET_MS 273
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// #define PULSE_COUNT_2 71
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// #define BIT_OFFSET_2_CYCLES 46
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// #define OVERRIDE_2_CYCLES 2
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// #endif
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// #endif
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/*------------------------------------------------------------------------------------------------
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Region Settings Section
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------------------------------------------------------------------------------------------------*/
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