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https://github.com/kalymos/PsNee.git
synced 2026-02-27 17:14:06 +00:00
BIOS patch neo SCPH-5000 SCPH-3500
This commit is contained in:
kalymos
@@ -75,122 +75,64 @@
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#endif
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#ifdef HIGH_PATCH_A
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#ifdef INTERRUPT_RISING
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ISR(PIN_AX_INTERRUPT_VECTOR) {
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/*
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* PHASE 3: Pulse Counting (Inside ISR)
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* The hardware Interrupt Service Routine (ISR) now takes over.
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* It counts the exact number of incoming pulses on PIN_AX until it
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* matches the PULSE_COUNT value.
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*/
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ISR(PIN_AY_INTERRUPT_VECTOR){
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pulse_counter++;
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if (pulse_counter == PULSE_COUNT){ // If pulse_counter reaches the value defined by PULSE_COUNT
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/*
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* PHASE 4: Precision Bit Alignment
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* Once the PULSE_COUNT is reached, a micro-delay (BIT_OFFSET) is applied.
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* This shifts the timing from the clock edge to the exact bit position
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* within the data stream that needs modification.
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*/
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_delay_us(BIT_OFFSET);
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/*
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* PHASE 5: Data Bus Overdrive (The Patch)
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* Briefly forcing PIN_DX to OUTPUT to pull the line and "nullify" the target bit.
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* This effectively overwrites the BIOS data on-the-fly
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* before reverting the pin to INPUT to release the bus.
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*/
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PIN_DX_OUTPUT;
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_delay_us (OVERRIDE);
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PIN_DX_INPUT;
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PIN_AX_INTERRUPT_DISABLE;
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pulse_counter = 0;
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patch_done = 1; // patch_done is set to 1, indicating that the first patch is completed.
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}
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PIN_LED_ON;
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PIN_LED_OFF;
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}
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void Bios_Patching(){
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/*
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* PHASE 1: Signal Stabilization & Alignment
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* Detects the startup state (Cold Boot vs. Reset).
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* If the line is already HIGH (Cold Boot), we wait for a full LOW-to-HIGH transition
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* to ensure we are aligned with the start of a clean clock cycle.
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*/
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if (PIN_AX_READ != 0) // Case: Power-on / Line high (---__-_-_)
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if (pulse_counter == PULSE_COUNT_2)
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{
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while (PIN_AX_READ != 0); // Wait for falling edge
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while (PIN_AX_READ == 0); // Wait for next rising edge to sync
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}
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else // Case: Reset / Line low (_____-_-_)
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{
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while (PIN_AX_READ == 0); // Wait for the very first rising edge
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}
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/*
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* PHASE 2: Address Bus Window Alignment
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* Introduces a BOOT_OFFSET delay to skip initial noise.
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* This aligns the execution window with a
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* known "idle gap" in the address bus activity, positioned
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* immediately before the target memory-access cycle.
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*
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* BOOT_OFFSET: |---------//---------|
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* AX LINE: -_-_-_-//-_-_-_-__________-_-_-_
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* BUS IDLE: |--------|
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*/
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_delay_ms(BOOT_OFFSET);
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// Armed for hardware detectio
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EIFR |=(1 << INTF0);
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PIN_AX_INTERRUPT_RISING;
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PIN_AX_INTERRUPT_ENABLE;
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while (patch_done != 1); // Wait for the first stage of the patch to complete:
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_delay_us (BIT_OFFSET_2);
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PIN_DX_OUTPUT;
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_delay_us (OVERRIDE_2);
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PIN_DX_INPUT;
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PIN_AY_INTERRUPT_DISABLE;
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}
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#endif
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#ifdef INTERRUPT_FALLING
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ISR(PIN_AX_INTERRUPT_VECTOR) {
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pulse_counter++;
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if (pulse_counter == PULSE_COUNT){
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_delay_us (BIT_OFFSET);
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PIN_DX_OUTPUT;
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_delay_us (OVERRIDE);
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PIN_DX_INPUT;
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PIN_AX_INTERRUPT_DISABLE;
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pulse_counter = 0;
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patch_done = 1;
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patch_done = 2;
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}
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}
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void Bios_Patching(){
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if (PIN_AX_READ != 0)
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PIN_DX_INPUT;
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cli(); // Disable interrupts for timing integrity
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if (PIN_AX_READ != 0)
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{
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while (PIN_AX_READ != 0);
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while (PIN_AX_READ == 0);
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while (PIN_AX_READ == 0);
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}
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else
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{
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while (PIN_AX_READ == 0);
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}
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_delay_ms(BOOT_OFFSET); /
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PIN_AX_INTERRUPT_FALLING;
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PIN_AX_INTERRUPT_ENABLE;
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_delay_ms(BOOT_OFFSET);
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PIN_LED_ON;
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_delay_us(BIT_OFFSET);
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PIN_DX_OUTPUT; // Force line (Low/High-Z override)
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_delay_us(OVERRIDE);
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PIN_DX_INPUT; // Release bus immediately
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PIN_LED_OFF;
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sei(); // Restore global interrupts
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while (patch_done != 1);
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while (patch_done != 1);
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PIN_LED_OFF;
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while (PIN_AY_READ != 0);
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_delay_ms(FOLLOWUP_OFFSET);
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PIN_AY_INTERRUPT_RISING;
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PIN_AY_INTERRUPT_ENABLE;
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while (patch_done != 2);
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}
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#endif
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#ifdef INTERRUPT_RISING_HIGH_PATCH
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@@ -236,14 +178,17 @@
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{
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while (PIN_AX_READ == 0);
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}
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_delay_ms(BOOT_OFFSET);
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_delay_ms(BOOT_OFFSET);
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PIN_LED_ON;
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PIN_AX_INTERRUPT_RISING;
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PIN_AX_INTERRUPT_ENABLE;
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while (patch_done != 1);
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while (patch_done != 1);
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PIN_LED_OFF;
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while (PIN_AY_READ != 0);
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_delay_ms(FOLLOWUP_OFFSET);
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@@ -47,10 +47,10 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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//#define SCPH_100 // DX - D0 | AX - A7 | | 4.3j - CRC F2AF798B
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//#define SCPH_7500_9000 // DX - D0 | AX - A7 | | 4.0j - CRC EC541CD0
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//#define SCPH_7000 // DX - D0 | AX - A7 | | 4.0j - CRC EC541CD0 Enables hardware support for disabling BIOS patching.
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#define SCPH_5500 // DX - D0 | AX - A5 | | 3.0j - CRC FF3EEB8C
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//#define SCPH_5500 // DX - D0 | AX - A5 | | 3.0j - CRC FF3EEB8C
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//#define SCPH_5000 // DX - D0 | AX - A5 | AX - A4 | 2.2j - CRC 24FC7E17
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//#define SCPH_3500 // DX - D0 | AX - A5 | AX - A4 | 2.1j - CRC BC190209
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//#define SCPH_3000 // DX - D5 | AX - A7, AY - A8 | AX - A6, AY - A7 | 1.1j - CRC 3539DEF6
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#define SCPH_3000 // DX - D5 | AX - A7, AY - A8 | AX - A6, AY - A7 | 1.1j - CRC 3539DEF6
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//#define SCPH_1000 // DX - D5 | AX - A7, AY - A8 | AX - A6, AY - A7 | 1.0j - CRC 3B601FC8
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/*------------------------------------------------------------------------------------------------
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@@ -85,22 +85,35 @@
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#ifdef SCPH_5000
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#define BIOS_PATCH
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#define INTERRUPT_FALLING
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#define TEST_BIOS
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#define LOW_TRIGGER
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#define BOOT_OFFSET 75.2 //75.12 - 75.27
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#define PULSE_COUNT 21
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#define BIT_OFFSET 2.8 //2.7 - 2.85
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#define OVERRIDE 0.1
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#define BIT_OFFSET 95.65
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#define OVERRIDE 0.2
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#endif
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#ifdef SCPH_3500
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#define BIOS_PATCH
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#define INTERRUPT_FALLING
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#define TEST_BIOS
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#define LOW_TRIGGER
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#define BOOT_OFFSET 75.2 //75.12 - 75.27
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#define PULSE_COUNT 21
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#define BIT_OFFSET 2.75 //2.65 - 2.85
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#define BIT_OFFSET 95.4
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#define OVERRIDE 0.2
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#endif
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// #ifdef SCPH_3000
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// #define BIOS_PATCH
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// #define HIGH_PATCH_A
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// #define BOOT_OFFSET 82.9 //82.65 - 83.26
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// #define BIT_OFFSET 278.65
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// #define OVERRIDE 0.15
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// #define HIGH_PATCH
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// #define FOLLOWUP_OFFSET 253.3
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// #define PULSE_COUNT_2 43
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// #define BIT_OFFSET_2 2.88
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// #define OVERRIDE_2 0.15
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// #endif
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#ifdef SCPH_3000
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#define BIOS_PATCH
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#define INTERRUPT_RISING_HIGH_PATCH
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