github.com/lisper.cpus-pdp8
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mirror of synced 2026-04-02 20:17:26 +00:00
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synthesis

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brad
2010-10-26 11:20:13 +00:00
parent 67880416ac
commit 8974fd8ff1
4 changed files with 32 additions and 6 deletions
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3
rtl/ide_disk.v
View File

@@ -398,8 +398,9 @@ module ide_disk(clk, reset,
ata_wr = 1;
ata_addr = ATA_DATA;
ata_in = {4'b0, buffer_in_hold};
`ifdef debug
$display("ide_disk: write1, %o", buffer_in_hold);
`endif
if (ata_done)
begin
if (wc == 8'h00)

16
rtl/pdp8.v
View File

@@ -668,11 +668,13 @@ module pdp8(clk, reset, initial_pc, pc_out, ac_out,
if (interrupt && interrupt_enable &&
!interrupt_inhibit && !interrupt_cycle)
begin
`ifdef debug
if (1)
$display("xxx interrupt, pc %o; %b %b %b; %b %b",
pc,
interrupt, interrupt_enable, interrupt_cycle,
interrupt_inhibit, interrupt_inhibit_delay);
`endif
interrupt_cycle <= 1;
interrupt <= 0;
interrupt_enable <= 0;
@@ -692,8 +694,10 @@ module pdp8(clk, reset, initial_pc, pc_out, ac_out,
begin
interrupt_cycle <= 0;
`ifdef debug
if (0)
$display("cpu: read ram [%o] -> %o", ram_addr, ram_data_in);
`endif
mb <= ram_data_in;
ir <= ram_data_in[11:9];
@@ -761,7 +765,9 @@ module pdp8(clk, reset, initial_pc, pc_out, ac_out,
if (iot && UF)
begin
UI <= 1;
$display("user iot: set UI");
`ifdef debug
$display("user iot: set UI");
`endif
end
if (iot && ~UF)
@@ -962,7 +968,9 @@ $display("user iot: set UI");
//
D0:
begin
`ifdef debug
if (0) $display("read ram [%o] -> %o", ram_addr, ram_data_in);
`endif
mb <= ram_data_in;
end
@@ -975,9 +983,11 @@ $display("user iot: set UI");
D2:
begin
`ifdef debug
// write ram
if (ram_wr)
if (0) $display("write ram [%o] <- %o", ram_addr, ram_data_out);
`endif
end
D3:
@@ -989,7 +999,9 @@ $display("user iot: set UI");
//
E0:
begin
`ifdef debug
if (0) $display("read ram [%o] -> %o", ram_addr, ram_data_in);
`endif
mb <= ram_data_in;
end
@@ -1012,9 +1024,11 @@ $display("user iot: set UI");
E2:
begin
// write ram
`ifdef debug
if (ram_wr)
if (0) $display("write ram [%o] <- %o (pc %o)",
ram_addr, ram_data_out, pc);
`endif
end
E3:

8
rtl/pdp8_tt.v
View File

@@ -249,13 +249,17 @@ tx_int <= 1'b0;
begin
if (assert_rx_int && ~rx_int)
begin
$display("xxx set rx_int");
`ifdef debug
$display("xxx set rx_int");
`endif
rx_int <= 1;
end
if (assert_tx_int && ~tx_int)
begin
$display("xxx set tx_int");
`ifdef debug
$display("xxx set tx_int");
`endif
tx_int <= 1;
end

11
rtl/top.v
View File

@@ -47,10 +47,13 @@ module top(rs232_txd, rs232_rxd,
output [1:0] ide_cs;
output [2:0] ide_da;
wire [15:0] ide_data_in;
wire [15:0] ide_data_out;
// -----------------------------------------------------------------
`ifndef sim_time
`define slower
// `define slower
`endif
`ifdef slower
@@ -177,10 +180,14 @@ module top(rs232_txd, rs232_rxd,
.ide_diow(ide_diow),
.ide_cs(ide_cs),
.ide_da(ide_da),
.ide_data_bus(ide_data_bus),
.ide_data_in(ide_data_in),
.ide_data_out(ide_data_out),
.rs232_in(rs232_rxd),
.rs232_out(rs232_txd));
assign ide_data_bus = ~ide_diow ? ide_data_out : 16'bz;
assign ide_data_in = ide_data_bus;
pdp8_ram ram(.clk(clk),
.reset(reset),
.addr(ram_addr),