fixed bugs so test_top.v works

verif/ram_s3board.v

@@ -82,6 +82,8 @@ module ram_s3board(ram_a, ram_oe_n, ram_we_n,
 	     ram1.ram_l[i] = 7'b0;
 	  end
 
+	n = 0;
+
 `ifdef verilator
  `define no_scan
 `endif
@@ -94,10 +96,13 @@ module ram_s3board(ram_a, ram_oe_n, ram_we_n,
        n = $scan$plusargs("test=", testfilename);
 `endif
 
-
-`ifdef no_scan
-	n = 0;
-`endif
+	if (n == 0)
+	  begin
+	     testfilename = "default.mem";
+	     $display("using default file");
+	     n = 1;
+	  end
+	
 	if (n > 0)
 	  begin
 	     $display("ram_s3board: code filename: %s", testfilename);

verif/test_top.v

@@ -2,6 +2,8 @@
 // testing top end for pdp8.v
 //
 
+`define sim_time 1
+
 `include "../rtl/ide.v"
 `include "../rtl/ide_disk.v"
 `include "../rtl/brg.v"
@@ -18,6 +20,7 @@
 `include "../rtl/bootrom.v"
 `include "../rtl/display.v"
 `include "../rtl/sevensegdecode.v"
+`include "../verif/ram_s3board.v"
 
 `timescale 1ns / 1ns
 
@@ -83,6 +86,16 @@ module test;
 	   .ide_cs(ide_cs),
 	   .ide_da(ide_da));
 
+    ram_s3board ram2(.ram_a(sram_a),
+		    .ram_oe_n(sram_oe_n),
+		    .ram_we_n(sram_we_n),
+		    .ram1_io(sram1_io),
+		    .ram1_ce_n(sram1_ce_n),
+		    .ram1_ub_n(sram1_ub_n), .ram1_lb_n(sram1_lb_n),
+		    .ram2_io(sram2_io),
+		    .ram2_ce_n(sram2_ce_n),
+		    .ram2_ub_n(sram2_ub_n), .ram2_lb_n(sram2_lb_n));
+
   initial
     begin
       $timeformat(-9, 0, "ns", 7);