github.com/lisper.cpus-pdp8
1
0
Fork 0
mirror of synced 2026-03-05 18:59:09 +00:00
Code Issues Releases Wiki Activity

Browse Source
This commit is contained in:
brad
2010-04-16 12:26:40 +00:00
parent 4e2201fcf8
commit e421d1a9f1
47 changed files with 1136 additions and 1693 deletions
Download Patch File Download Diff File Expand all files Collapse all files

BIN
xilinx/pdp8/__ISE_repository_pdp8.ise_.lock
View File

Binary file not shown.

2
xilinx/pdp8/_ngo/netlist.lst
View File

@@ -1,2 +1,2 @@
/home/brad/pdp8/xilinx/pdp8/top.ngc 1271286191
/home/brad/pdp8/xilinx/pdp8/top.ngc 1271420145
OK

8
xilinx/pdp8/_xmsgs/map.xmsgs
View File

@@ -37,7 +37,13 @@ BUFGP symbol &quot;sysclk_BUFGP&quot; (output signal=sysclk_BUFGP)</arg>
<arg fmt="%s" index="2">Pin D of io/tt/baud_rate_generator/rx_baud_clk</arg>
</msg>
<msg type="warning" file="Pack" num="266" delta="unknown" >The function generator <arg fmt="%s" index="1">cpu/_mux0009&lt;0&gt;711</arg> failed to merge with F5 multiplexer <arg fmt="%s" index="2">cpu/_mux0009&lt;4&gt;199_SW1</arg>. <arg fmt="%z" index="3">There is a conflict for the FXMUX.</arg> The design will exhibit suboptimal timing.
<msg type="warning" file="Pack" num="266" delta="unknown" >The function generator <arg fmt="%s" index="1">cpu/_mux0009&lt;4&gt;129</arg> failed to merge with F5 multiplexer <arg fmt="%s" index="2">cpu/_mux0009&lt;7&gt;73_SW11_f5</arg>. <arg fmt="%z" index="3">There is a conflict for the FXMUX.</arg> The design will exhibit suboptimal timing.
</msg>
<msg type="warning" file="Pack" num="266" delta="unknown" >The function generator <arg fmt="%s" index="1">cpu/_mux0009&lt;4&gt;129</arg> failed to merge with F5 multiplexer <arg fmt="%s" index="2">cpu/_mux0009&lt;8&gt;73_SW11_f5</arg>. <arg fmt="%z" index="3">There is a conflict for the FXMUX.</arg> The design will exhibit suboptimal timing.
</msg>
<msg type="warning" file="Pack" num="266" delta="unknown" >The function generator <arg fmt="%s" index="1">cpu/_mux0009&lt;4&gt;129</arg> failed to merge with F5 multiplexer <arg fmt="%s" index="2">cpu/_mux0009&lt;6&gt;73_SW1</arg>. <arg fmt="%z" index="3">There is a conflict for the FXMUX.</arg> The design will exhibit suboptimal timing.
</msg>
</messages>

4
xilinx/pdp8/_xmsgs/par.xmsgs
View File

@@ -8,10 +8,10 @@
<msg type="info" file="Par" num="282" delta="unknown" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;. For a balance between the fastest runtime and best performance, set the effort level to &quot;med&quot;.
</msg>
<msg type="warning" file="Route" num="447" delta="unknown" >CLK Net:<arg fmt="%s" index="1">io/kw/kw_src_clk</arg> may have excessive skew because
<msg type="warning" file="Route" num="447" delta="unknown" >CLK Net:<arg fmt="%s" index="1">io/tt/baud_rate_generator/tx_baud_clk</arg> may have excessive skew because
</msg>
<msg type="warning" file="Route" num="447" delta="unknown" >CLK Net:<arg fmt="%s" index="1">io/tt/baud_rate_generator/tx_baud_clk</arg> may have excessive skew because
<msg type="warning" file="Route" num="447" delta="unknown" >CLK Net:<arg fmt="%s" index="1">io/kw/kw_src_clk</arg> may have excessive skew because
</msg>
<msg type="warning" file="Route" num="447" delta="unknown" >CLK Net:<arg fmt="%s" index="1">io/tt/baud_rate_generator/rx_baud_clk</arg> may have excessive skew because

3
xilinx/pdp8/_xmsgs/xst.xmsgs
View File

@@ -71,9 +71,6 @@
<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">mb&lt;11:3&gt;</arg>&gt; is never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">db_done</arg>&gt; is assigned but never used.
</msg>
<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">ide_error</arg>&gt; is assigned but never used.
</msg>

557
xilinx/pdp8/device_usage_statistics.html
View File

@@ -1,557 +0,0 @@
<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<H3>Device Usage Page (device_usage_statistics.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx. The file also contains predefined XML tags used to simplify processing.<BR>&nbsp;<BR>Please verify the contents are okay to send to Xilinx!<BR>&nbsp;<BR><HR>&nbsp;<BR>
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>Software Version and Target Device</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD>
<TD><xtag-property name="ProductVersion">ISE:8.2i</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Family:</B></TD>
<TD><xtag-property name="TargetFamily">spartan3</xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>OS Platform:</B></TD>
<TD><xtag-property name="OSPlatform">LIN64</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD><xtag-property name="TargetDevice">xc3s1000</xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
<TD><xtag-property name="ProjectID">17753</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
<TD><xtag-property name="TargetPackage">ft256</xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
<TD><xtag-property name="Date Generated">Wed Apr 14 19:10:12 2010</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Speed:</B></TD>
<TD><xtag-property name="TargetSpeed">-5</xtag-property></TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Device Usage Statistics</B></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'><TD><B>Macro Statistics</B></TD><TD><B>Miscellaneous Statistics</B></TD><TD><B>Net Statistics</B></TD><TD><B>Site Usage</B></TD></TR><TR VALIGN=TOP>
<xtag-section name="MacroStatistics">
<TD>
<xtag-group><xtag-group-name name=" Registers=334"> Registers=334</xtag-group-name>
<UL>
<LI><xtag-item1>Flip-Flops=334</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name=" Multiplexers=9"> Multiplexers=9</xtag-group-name>
<UL>
<LI><xtag-item1>1-bit 4-to-1 multiplexer=5</xtag-item1></LI>
<LI><xtag-item1>12-bit 4-to-1 multiplexer=2</xtag-item1></LI>
<LI><xtag-item1>3-bit 4-to-1 multiplexer=1</xtag-item1></LI>
<LI><xtag-item1>4-bit 4-to-1 multiplexer=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name=" RAMs=1"> RAMs=1</xtag-group-name>
<UL>
<LI><xtag-item1>256x12-bit single-port distributed RAM=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name=" ROMs=6"> ROMs=6</xtag-group-name>
<UL>
<LI><xtag-item1>16x25-bit ROM=1</xtag-item1></LI>
<LI><xtag-item1>4x1-bit ROM=4</xtag-item1></LI>
<LI><xtag-item1>8x8-bit ROM=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name=" FSMs=7"> FSMs=7</xtag-group-name>
</xtag-group>
<xtag-group><xtag-group-name name=" Xors=1"> Xors=1</xtag-group-name>
<UL>
<LI><xtag-item1>1-bit xor2=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name=" Adders/Subtractors=11"> Adders/Subtractors=11</xtag-group-name>
<UL>
<LI><xtag-item1>12-bit adder=4</xtag-item1></LI>
<LI><xtag-item1>12-bit adder carry out=2</xtag-item1></LI>
<LI><xtag-item1>13-bit adder=2</xtag-item1></LI>
<LI><xtag-item1>15-bit adder=1</xtag-item1></LI>
<LI><xtag-item1>20-bit adder=1</xtag-item1></LI>
<LI><xtag-item1>4-bit adder=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name=" Counters=11"> Counters=11</xtag-group-name>
<UL>
<LI><xtag-item1>11-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>12-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>13-bit up counter=2</xtag-item1></LI>
<LI><xtag-item1>15-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>2-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>25-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>4-bit up counter=2</xtag-item1></LI>
<LI><xtag-item1>8-bit up counter=2</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name=" Comparators=4"> Comparators=4</xtag-group-name>
<UL>
<LI><xtag-item1>12-bit comparator equal=1</xtag-item1></LI>
<LI><xtag-item1>25-bit comparator equal=1</xtag-item1></LI>
<LI><xtag-item1>4-bit comparator greatequal=1</xtag-item1></LI>
<LI><xtag-item1>4-bit comparator lessequal=1</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
</xtag-section>
<xtag-section name="DesignStatistics">
<TD>
<xtag-group><xtag-group-name name="MiscellaneousStatistics">MiscellaneousStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>AVG_LUT_FAN_IN=3.578600</xtag-item1></LI>
<LI><xtag-item1>AVG_SIG_FANOUT=2.980000</xtag-item1></LI>
<LI><xtag-item1>FOUR_LOAD_SIG=27</xtag-item1></LI>
<LI><xtag-item1>LUT=1374</xtag-item1></LI>
<LI><xtag-item1>MAX_SIG_FANOUT=441</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_4_INPUT_LUTS=1374</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_4_INPUT_LUT_RTS=183</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_BONDED_IOBS=89</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_CYINIT=123</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_CYMUX=221</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_EQUIV_GATES=38</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_IOB_FFS=14</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_JTAG_GATES=89</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_LUTLESS_IOB_FFS=14</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_LUTLESS_SLICE_FFS=206</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_MUXF5=133</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_MUXF6=12</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_MUXFS=241</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_RAM32S=96</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_SLICELS=949</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_SLICEMS=96</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_SLICES=1045</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_SLICE_FFS=492</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_TOTAL_LUTLESS_REGISTERS=220</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_XBZ_GCLKS=3</xtag-item1></LI>
<LI><xtag-item1>PK_NUM_XOR=202</xtag-item1></LI>
<LI><xtag-item1>SINGLE_LOAD_SIG=1035</xtag-item1></LI>
<LI><xtag-item1>THREE_LOAD_SIG=41</xtag-item1></LI>
<LI><xtag-item1>TWO_LOAD_SIG=112</xtag-item1></LI>
</UL>
</xtag-group>
</TD><TD>
<xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>NumNets_Active=1923</xtag-item1></LI>
<LI><xtag-item1>NumNets_Gnd=1</xtag-item1></LI>
<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=496</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=630</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=4456</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DUMMY=5883</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DUMMYESC=17</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=110</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_HFULLHEX=60</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_HLONG=7</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_HUNIHEX=300</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=6652</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=31</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OMUX=1853</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=1804</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PREBXBY=1668</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_VFULLHEX=233</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_VLONG=54</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_VUNIHEX=354</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_DOUBLE=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_INPUT=50</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_OMUX=46</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_OUTPUT=37</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Gnd_PREBXBY=22</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
</xtag-section>
<xtag-section name="DeviceUsage">
<TD>
<xtag-group><xtag-group-name name="SiteSummary">SiteSummary</xtag-group-name>
<UL>
<LI><xtag-item2>BUFGMUX=3</xtag-item2></LI>
<LI><xtag-item2>BUFGMUX_GCLKMUX=3</xtag-item2></LI>
<LI><xtag-item2>BUFGMUX_GCLK_BUFFER=3</xtag-item2></LI>
<LI><xtag-item2>IOB=89</xtag-item2></LI>
<LI><xtag-item2>IOB_DELAY=14</xtag-item2></LI>
<LI><xtag-item2>IOB_IFF1=14</xtag-item2></LI>
<LI><xtag-item2>IOB_INBUF=31</xtag-item2></LI>
<LI><xtag-item2>IOB_OUTBUF=82</xtag-item2></LI>
<LI><xtag-item2>IOB_PAD=89</xtag-item2></LI>
<LI><xtag-item2>SLICEL=949</xtag-item2></LI>
<LI><xtag-item2>SLICEL_C1VDD=15</xtag-item2></LI>
<LI><xtag-item2>SLICEL_CYMUXF=115</xtag-item2></LI>
<LI><xtag-item2>SLICEL_CYMUXG=106</xtag-item2></LI>
<LI><xtag-item2>SLICEL_F=781</xtag-item2></LI>
<LI><xtag-item2>SLICEL_F5MUX=133</xtag-item2></LI>
<LI><xtag-item2>SLICEL_F6MUX=12</xtag-item2></LI>
<LI><xtag-item2>SLICEL_FFX=226</xtag-item2></LI>
<LI><xtag-item2>SLICEL_FFY=266</xtag-item2></LI>
<LI><xtag-item2>SLICEL_G=785</xtag-item2></LI>
<LI><xtag-item2>SLICEL_GNDF=94</xtag-item2></LI>
<LI><xtag-item2>SLICEL_GNDG=100</xtag-item2></LI>
<LI><xtag-item2>SLICEL_XORF=97</xtag-item2></LI>
<LI><xtag-item2>SLICEL_XORG=105</xtag-item2></LI>
<LI><xtag-item2>SLICEM=96</xtag-item2></LI>
<LI><xtag-item2>SLICEM_F=96</xtag-item2></LI>
<LI><xtag-item2>SLICEM_F5MUX=96</xtag-item2></LI>
<LI><xtag-item2>SLICEM_G=96</xtag-item2></LI>
<LI><xtag-item2>SLICEM_WSGEN=96</xtag-item2></LI>
</UL>
</xtag-group>
</TD>
</xtag-section>
</TR></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Configuration Data</B></TD></TR><TR VALIGN=TOP>
<xtag-section name="ReportConfigData">
<TD>
<xtag-group><xtag-group-name name="BUFGMUX_GCLKMUX">BUFGMUX_GCLKMUX</xtag-group-name>
<UL>
<LI><xtag-item3>DISABLE_ATTR=[LOW:3]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_IFF1">IOB_IFF1</xtag-group-name>
<UL>
<LI><xtag-item3>IFF1_INIT_ATTR=[INIT0:13] [INIT1:1]</xtag-item3></LI>
<LI><xtag-item3>IFF1_SR_ATTR=[SRLOW:12] [SRHIGH:1]</xtag-item3></LI>
<LI><xtag-item3>IFFATTRBOX=[ASYNC:1] [SYNC:12]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:14]</xtag-item3></LI>
</UL>
</TD><TD>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_PAD">IOB_PAD</xtag-group-name>
<UL>
<LI><xtag-item3>DRIVEATTRBOX=[12:82]</xtag-item3></LI>
<LI><xtag-item3>IOATTRBOX=[LVCMOS25:89]</xtag-item3></LI>
<LI><xtag-item3>SLEW=[SLOW:82]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_FFX">SLICEL_FFX</xtag-group-name>
<UL>
<LI><xtag-item3>FFX_INIT_ATTR=[INIT0:216] [INIT1:10]</xtag-item3></LI>
<LI><xtag-item3>FFX_SR_ATTR=[SRLOW:216] [SRHIGH:10]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:226]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:52] [SYNC:174]</xtag-item3></LI>
</UL>
</TD><TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_FFY">SLICEL_FFY</xtag-group-name>
<UL>
<LI><xtag-item3>FFY_INIT_ATTR=[INIT0:256] [INIT1:10]</xtag-item3></LI>
<LI><xtag-item3>FFY_SR_ATTR=[SRLOW:256] [SRHIGH:10]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:266]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:69] [SYNC:197]</xtag-item3></LI>
</UL>
</TD><TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEM_F">SLICEM_F</xtag-group-name>
<UL>
<LI><xtag-item3>LUT_OR_MEM=[RAM:96]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEM_G">SLICEM_G</xtag-group-name>
<UL>
<LI><xtag-item3>LUT_OR_MEM=[RAM:96]</xtag-item3></LI>
</UL>
</xtag-group>
</TD>
</xtag-section>
</TR></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Pin Data</B></TD></TR><TR VALIGN=TOP>
<xtag-section name="ReportConfigData">
<TD>
<xtag-group><xtag-group-name name="BUFGMUX">BUFGMUX</xtag-group-name>
<UL>
<LI><xtag-item1>I0=3</xtag-item1></LI>
<LI><xtag-item1>O=3</xtag-item1></LI>
<LI><xtag-item1>S=3</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="BUFGMUX_GCLKMUX">BUFGMUX_GCLKMUX</xtag-group-name>
<UL>
<LI><xtag-item1>I0=3</xtag-item1></LI>
<LI><xtag-item1>OUT=3</xtag-item1></LI>
<LI><xtag-item1>S=3</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="BUFGMUX_GCLK_BUFFER">BUFGMUX_GCLK_BUFFER</xtag-group-name>
<UL>
<LI><xtag-item1>IN=3</xtag-item1></LI>
<LI><xtag-item1>OUT=3</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB">IOB</xtag-group-name>
<UL>
<LI><xtag-item1>I=17</xtag-item1></LI>
<LI><xtag-item1>ICE=12</xtag-item1></LI>
<LI><xtag-item1>ICLK1=14</xtag-item1></LI>
<LI><xtag-item1>IQ1=14</xtag-item1></LI>
<LI><xtag-item1>O1=82</xtag-item1></LI>
<LI><xtag-item1>PAD=89</xtag-item1></LI>
<LI><xtag-item1>SR=13</xtag-item1></LI>
<LI><xtag-item1>T1=32</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_DELAY">IOB_DELAY</xtag-group-name>
<UL>
<LI><xtag-item1>IN=14</xtag-item1></LI>
<LI><xtag-item1>OUT=14</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_IFF1">IOB_IFF1</xtag-group-name>
<UL>
<LI><xtag-item1>CE=12</xtag-item1></LI>
<LI><xtag-item1>CK=14</xtag-item1></LI>
<LI><xtag-item1>D=14</xtag-item1></LI>
<LI><xtag-item1>Q=14</xtag-item1></LI>
<LI><xtag-item1>SR=13</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_INBUF">IOB_INBUF</xtag-group-name>
<UL>
<LI><xtag-item1>IN=31</xtag-item1></LI>
<LI><xtag-item1>OUT=31</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name>
<UL>
<LI><xtag-item1>IN=82</xtag-item1></LI>
<LI><xtag-item1>OUT=82</xtag-item1></LI>
<LI><xtag-item1>TRI=32</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_PAD">IOB_PAD</xtag-group-name>
<UL>
<LI><xtag-item1>PAD=89</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item1>BX=221</xtag-item1></LI>
<LI><xtag-item1>BY=215</xtag-item1></LI>
<LI><xtag-item1>CE=114</xtag-item1></LI>
<LI><xtag-item1>CIN=105</xtag-item1></LI>
<LI><xtag-item1>CLK=386</xtag-item1></LI>
<LI><xtag-item1>COUT=106</xtag-item1></LI>
<LI><xtag-item1>F1=773</xtag-item1></LI>
<LI><xtag-item1>F2=671</xtag-item1></LI>
<LI><xtag-item1>F3=630</xtag-item1></LI>
<LI><xtag-item1>F4=494</xtag-item1></LI>
<LI><xtag-item1>F5=24</xtag-item1></LI>
<LI><xtag-item1>FXINA=12</xtag-item1></LI>
<LI><xtag-item1>FXINB=12</xtag-item1></LI>
<LI><xtag-item1>G1=784</xtag-item1></LI>
<LI><xtag-item1>G2=689</xtag-item1></LI>
<LI><xtag-item1>G3=589</xtag-item1></LI>
<LI><xtag-item1>G4=470</xtag-item1></LI>
<LI><xtag-item1>SR=363</xtag-item1></LI>
<LI><xtag-item1>X=586</xtag-item1></LI>
<LI><xtag-item1>XB=1</xtag-item1></LI>
<LI><xtag-item1>XQ=226</xtag-item1></LI>
<LI><xtag-item1>Y=495</xtag-item1></LI>
<LI><xtag-item1>YQ=266</xtag-item1></LI>
</UL>
</TD><TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_C1VDD">SLICEL_C1VDD</xtag-group-name>
<UL>
<LI><xtag-item1>1=15</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_CYMUXF">SLICEL_CYMUXF</xtag-group-name>
<UL>
<LI><xtag-item1>0=115</xtag-item1></LI>
<LI><xtag-item1>1=115</xtag-item1></LI>
<LI><xtag-item1>OUT=115</xtag-item1></LI>
<LI><xtag-item1>S0=115</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_CYMUXG">SLICEL_CYMUXG</xtag-group-name>
<UL>
<LI><xtag-item1>0=106</xtag-item1></LI>
<LI><xtag-item1>1=106</xtag-item1></LI>
<LI><xtag-item1>OUT=106</xtag-item1></LI>
<LI><xtag-item1>S0=106</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_F">SLICEL_F</xtag-group-name>
<UL>
<LI><xtag-item1>A1=773</xtag-item1></LI>
<LI><xtag-item1>A2=671</xtag-item1></LI>
<LI><xtag-item1>A3=630</xtag-item1></LI>
<LI><xtag-item1>A4=494</xtag-item1></LI>
<LI><xtag-item1>D=781</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_F5MUX">SLICEL_F5MUX</xtag-group-name>
<UL>
<LI><xtag-item1>F=133</xtag-item1></LI>
<LI><xtag-item1>G=133</xtag-item1></LI>
<LI><xtag-item1>OUT=133</xtag-item1></LI>
<LI><xtag-item1>S0=133</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_F6MUX">SLICEL_F6MUX</xtag-group-name>
<UL>
<LI><xtag-item1>0=12</xtag-item1></LI>
<LI><xtag-item1>1=12</xtag-item1></LI>
<LI><xtag-item1>OUT=12</xtag-item1></LI>
<LI><xtag-item1>S0=12</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_FFX">SLICEL_FFX</xtag-group-name>
<UL>
<LI><xtag-item1>CE=59</xtag-item1></LI>
<LI><xtag-item1>CK=226</xtag-item1></LI>
<LI><xtag-item1>D=226</xtag-item1></LI>
<LI><xtag-item1>Q=226</xtag-item1></LI>
<LI><xtag-item1>REV=42</xtag-item1></LI>
<LI><xtag-item1>SR=212</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_FFY">SLICEL_FFY</xtag-group-name>
<UL>
<LI><xtag-item1>CE=101</xtag-item1></LI>
<LI><xtag-item1>CK=266</xtag-item1></LI>
<LI><xtag-item1>D=266</xtag-item1></LI>
<LI><xtag-item1>Q=266</xtag-item1></LI>
<LI><xtag-item1>REV=71</xtag-item1></LI>
<LI><xtag-item1>SR=244</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_G">SLICEL_G</xtag-group-name>
<UL>
<LI><xtag-item1>A1=784</xtag-item1></LI>
<LI><xtag-item1>A2=689</xtag-item1></LI>
<LI><xtag-item1>A3=589</xtag-item1></LI>
<LI><xtag-item1>A4=470</xtag-item1></LI>
<LI><xtag-item1>D=785</xtag-item1></LI>
</UL>
</TD><TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_GNDF">SLICEL_GNDF</xtag-group-name>
<UL>
<LI><xtag-item1>0=94</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_GNDG">SLICEL_GNDG</xtag-group-name>
<UL>
<LI><xtag-item1>0=100</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_XORF">SLICEL_XORF</xtag-group-name>
<UL>
<LI><xtag-item1>0=97</xtag-item1></LI>
<LI><xtag-item1>1=97</xtag-item1></LI>
<LI><xtag-item1>O=97</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL_XORG">SLICEL_XORG</xtag-group-name>
<UL>
<LI><xtag-item1>0=105</xtag-item1></LI>
<LI><xtag-item1>1=105</xtag-item1></LI>
<LI><xtag-item1>O=105</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name>
<UL>
<LI><xtag-item1>BX=96</xtag-item1></LI>
<LI><xtag-item1>BY=96</xtag-item1></LI>
<LI><xtag-item1>CLK=96</xtag-item1></LI>
<LI><xtag-item1>F1=96</xtag-item1></LI>
<LI><xtag-item1>F2=96</xtag-item1></LI>
<LI><xtag-item1>F3=96</xtag-item1></LI>
<LI><xtag-item1>F4=96</xtag-item1></LI>
<LI><xtag-item1>G1=96</xtag-item1></LI>
<LI><xtag-item1>G2=96</xtag-item1></LI>
<LI><xtag-item1>G3=96</xtag-item1></LI>
<LI><xtag-item1>G4=96</xtag-item1></LI>
<LI><xtag-item1>SR=96</xtag-item1></LI>
<LI><xtag-item1>X=96</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEM_F">SLICEM_F</xtag-group-name>
<UL>
<LI><xtag-item1>A1=96</xtag-item1></LI>
<LI><xtag-item1>A2=96</xtag-item1></LI>
<LI><xtag-item1>A3=96</xtag-item1></LI>
<LI><xtag-item1>A4=96</xtag-item1></LI>
<LI><xtag-item1>D=96</xtag-item1></LI>
<LI><xtag-item1>DI=96</xtag-item1></LI>
<LI><xtag-item1>WF1=96</xtag-item1></LI>
<LI><xtag-item1>WF2=96</xtag-item1></LI>
<LI><xtag-item1>WF3=96</xtag-item1></LI>
<LI><xtag-item1>WF4=96</xtag-item1></LI>
<LI><xtag-item1>WS=96</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEM_F5MUX">SLICEM_F5MUX</xtag-group-name>
<UL>
<LI><xtag-item1>F=96</xtag-item1></LI>
<LI><xtag-item1>G=96</xtag-item1></LI>
<LI><xtag-item1>OUT=96</xtag-item1></LI>
<LI><xtag-item1>S0=96</xtag-item1></LI>
</UL>
</TD><TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEM_G">SLICEM_G</xtag-group-name>
<UL>
<LI><xtag-item1>A1=96</xtag-item1></LI>
<LI><xtag-item1>A2=96</xtag-item1></LI>
<LI><xtag-item1>A3=96</xtag-item1></LI>
<LI><xtag-item1>A4=96</xtag-item1></LI>
<LI><xtag-item1>D=96</xtag-item1></LI>
<LI><xtag-item1>DI=96</xtag-item1></LI>
<LI><xtag-item1>WG1=96</xtag-item1></LI>
<LI><xtag-item1>WG2=96</xtag-item1></LI>
<LI><xtag-item1>WG3=96</xtag-item1></LI>
<LI><xtag-item1>WG4=96</xtag-item1></LI>
<LI><xtag-item1>WS=96</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEM_WSGEN">SLICEM_WSGEN</xtag-group-name>
<UL>
<LI><xtag-item1>CK=96</xtag-item1></LI>
<LI><xtag-item1>WE=96</xtag-item1></LI>
<LI><xtag-item1>WE0=96</xtag-item1></LI>
<LI><xtag-item1>WSF=96</xtag-item1></LI>
<LI><xtag-item1>WSG=96</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
</xtag-section>
</TR></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD><B>Tool Usage</B></TD></TR>
<TR VALIGN=TOP><TD ALIGN=LEFT>Command Line History<xtag-section name="CommandLineLog"><UL>
<LI><xtag-cmdline>xst -ise &lt;ise_file&gt; -intstyle ise -ifn &lt;fname&gt;.xst -ofn &lt;fname&gt;.syr</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -ise &lt;ise_file&gt; -intstyle ise -ifn &lt;fname&gt;.xst -ofn &lt;fname&gt;.syr</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -ise &lt;ise_file&gt; -intstyle ise -ifn &lt;fname&gt;.xst -ofn &lt;fname&gt;.syr</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -ise &lt;ise_file&gt; -intstyle ise -ifn &lt;fname&gt;.xst -ofn &lt;fname&gt;.syr</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -ise &lt;ise_file&gt; -intstyle ise -ifn &lt;fname&gt;.xst -ofn &lt;fname&gt;.syr</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -ise &lt;ise_file&gt; -intstyle ise -ifn &lt;fname&gt;.xst -ofn &lt;fname&gt;.syr</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -ise &lt;ise_file&gt; -intstyle ise -ifn &lt;fname&gt;.xst -ofn &lt;fname&gt;.syr</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -ise &lt;ise_file&gt; -intstyle ise -ifn &lt;fname&gt;.xst -ofn &lt;fname&gt;.syr</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -ise &lt;ise_file&gt; -intstyle ise -ifn &lt;fname&gt;.xst -ofn &lt;fname&gt;.syr</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -ise &lt;ise_file&gt; -intstyle ise -ifn &lt;fname&gt;.xst -ofn &lt;fname&gt;.syr</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -ise &lt;ise_file&gt; -intstyle ise -ifn &lt;fname&gt;.xst -ofn &lt;fname&gt;.syr</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -ise &lt;ise_file&gt; -intstyle ise -ifn &lt;fname&gt;.xst -ofn &lt;fname&gt;.syr</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -ise &lt;ise_file&gt; &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -ise &lt;ise_file&gt; -intstyle ise -p xc3s1000-ft256-5 -cm area -pr b -k 4 -c 100 -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -ise &lt;ise_file&gt; -w -intstyle ise -ol std -t 1 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -ise &lt;ise_file&gt; -intstyle ise -e 3 -l 3 -s 5 -xml &lt;design&gt; &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -ise &lt;ise_file&gt; -intstyle ise -ifn &lt;fname&gt;.xst -ofn &lt;fname&gt;.syr</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -ise &lt;ise_file&gt; -intstyle ise -ifn &lt;fname&gt;.xst -ofn &lt;fname&gt;.syr</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -ise &lt;ise_file&gt; -intstyle ise -ifn &lt;fname&gt;.xst -ofn &lt;fname&gt;.syr</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -ise &lt;ise_file&gt; &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -ise &lt;ise_file&gt; -intstyle ise -p xc3s1000-ft256-5 -cm area -pr b -k 4 -c 100 -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -ise &lt;ise_file&gt; -intstyle ise -ifn &lt;fname&gt;.xst -ofn &lt;fname&gt;.syr</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -ise &lt;ise_file&gt; &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -ise &lt;ise_file&gt; -intstyle ise -p xc3s1000-ft256-5 -cm area -pr b -k 4 -c 100 -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -ise &lt;ise_file&gt; -w -intstyle ise -ol std -t 1 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -ise &lt;ise_file&gt; -intstyle ise -e 3 -l 3 -s 5 -xml &lt;design&gt; &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -ise &lt;ise_file&gt; -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
</xtag-section></UL></TD></TR>
</TABLE>
</BODY></HTML>

BIN
xilinx/pdp8/pdp8.ise
View File

Binary file not shown.

BIN
xilinx/pdp8/pdp8.ise_ISE_Backup
View File

Binary file not shown.

24
xilinx/pdp8/pdp8.ntrc_log
View File

@@ -1,27 +1,3 @@
--------------------
Xst NTRC: "/top" : OUT_OF_DATE
--------------------
Xst NTRC: "/top" : OUT_OF_DATE
--------------------
Xst NTRC: "/top" : OUT_OF_DATE
--------------------
Xst NTRC: "/top" : OUT_OF_DATE
--------------------
Xst NTRC: "/top" : OUT_OF_DATE
--------------------
Xst NTRC: "/top" : OUT_OF_DATE
--------------------
Xst NTRC: "/top" : OUT_OF_DATE
--------------------
Xst NTRC: "/top" : OUT_OF_DATE
--------------------
Xst NTRC: "/top" : OUT_OF_DATE
--------------------
Xst NTRC: "/top" : OUT_OF_DATE
--------------------
Map NTRC: "/top" : OUT_OF_DATE
--------------------
Xst NTRC: "/top" : OUT_OF_DATE
--------------------
Xst NTRC: "/top" : OUT_OF_DATE
--------------------

1
xilinx/pdp8/ram_32kx12.prj
View File

@@ -1 +0,0 @@
verilog work "../../rtl/ram_32kx12.v"

27
xilinx/pdp8/ram_32kx12.stx
View File

@@ -1,27 +0,0 @@
Release 8.2i - xst I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.07 s | Elapsed : 0.00 / 0.00 s
-->
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "../../rtl/ram_32kx12.v" in library work
Module <ram_32kx12> compiled
No errors in compilation
Analysis of file <"ram_32kx12.prj"> succeeded.
CPU : 0.07 / 0.14 s | Elapsed : 0.00 / 0.00 s
-->
Total memory usage is 205440 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

4
xilinx/pdp8/ram_32kx12.xst
View File

@@ -1,4 +0,0 @@
set -tmpdir "./xst/projnav.tmp"
elaborate
-ifn ram_32kx12.prj
-ifmt mixed

0
xilinx/pdp8/ram_32kx12_vhdl.prj
View File

2
xilinx/pdp8/top.bgn
View File

@@ -5,7 +5,7 @@ Loading device for application Rf_Device from file '3s1000.nph' in environment
"top" is an NCD, version 3.1, device xc3s1000, package ft256, speed -5
Opened constraints file top.pcf.
Wed Apr 14 19:10:00 2010
Fri Apr 16 08:19:36 2010
bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:6 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Match_cycle:Auto -g Security:None -g DonePipe:No -g DriveDone:No top.ncd

BIN
xilinx/pdp8/top.bit
View File

Binary file not shown.

2
xilinx/pdp8/top.bld
View File

@@ -21,7 +21,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 247072 kilobytes
Total memory usage is 247480 kilobytes
Writing NGD file "top.ngd" ...

16
xilinx/pdp8/top.cmd_log
View File

@@ -1,25 +1,9 @@
xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
xst -ise "C:/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
xst -ise "/home/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
ngdbuild -ise "/home/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc3s1000-ft256-5 "top.ngc" top.ngd
map -ise "/home/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -p xc3s1000-ft256-5 -cm area -pr b -k 4 -c 100 -o top_map.ncd top.ngd top.pcf
par -ise "/home/brad/pdp8/xilinx/pdp8/pdp8.ise" -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd top.pcf
trce -ise "/home/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -e 3 -l 3 -s 5 -xml top top.ncd -o top.twr top.pcf
xst -ise "/home/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
xst -ise "/home/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
xst -ise "/home/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
ngdbuild -ise "/home/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc3s1000-ft256-5 "top.ngc" top.ngd
map -ise "/home/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -p xc3s1000-ft256-5 -cm area -pr b -k 4 -c 100 -o top_map.ncd top.ngd top.pcf
xst -ise "/home/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -ifn top.xst -ofn top.syr
ngdbuild -ise "/home/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc3s1000-ft256-5 "top.ngc" top.ngd
map -ise "/home/brad/pdp8/xilinx/pdp8/pdp8.ise" -intstyle ise -p xc3s1000-ft256-5 -cm area -pr b -k 4 -c 100 -o top_map.ncd top.ngd top.pcf
par -ise "/home/brad/pdp8/xilinx/pdp8/pdp8.ise" -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd top.pcf

2
xilinx/pdp8/top.lso
View File

@@ -1 +1 @@
work
work

2
xilinx/pdp8/top.ncd
View File

File diff suppressed because one or more lines are too long

2
xilinx/pdp8/top.ngc
View File

File diff suppressed because one or more lines are too long

2
xilinx/pdp8/top.ngd
View File

File diff suppressed because one or more lines are too long

2
xilinx/pdp8/top.ngr
View File

File diff suppressed because one or more lines are too long

238
xilinx/pdp8/top.pad
View File

@@ -1,7 +1,7 @@
Release 8.2i - par I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
Wed Apr 14 19:04:43 2010
Fri Apr 16 08:17:40 2010
# NOTE: This file is designed to be imported into a spreadsheet program
@@ -26,11 +26,11 @@ A4||DIFFM|IO_L01P_0/VRN_0|UNUSED||0||||||||||
A5||IOB|IO|UNUSED||0||||||||||
A6|||VCCAUX||||||||2.5|||||
A7||IOB|IO|UNUSED||0||||||||||
A8|sram1_io<13>|IOB|IO_L32P_0/GCLK6|TRISTATE|LVCMOS25|0|12|SLOW|NONE**|||||NO|NONE|
A9|sram1_io<8>|IOB|IO|BIDIR|LVCMOS25|1|12|SLOW|NONE**|NONE||||NO|NONE|
A10|sram_oe_n|IOB|IO_L31N_1/VREF_1|OUTPUT|LVCMOS25|1|12|SLOW|NONE**|||||NO|NONE|
A8||DIFFM|IO_L32P_0/GCLK6|UNUSED||0||||||||||
A9||IOB|IO|UNUSED||1||||||||||
A10||DIFFS|IO_L31N_1/VREF_1|UNUSED||1||||||||||
A11|||VCCAUX||||||||2.5|||||
A12|sram1_io<4>|IOB|IO|BIDIR|LVCMOS25|1|12|SLOW|NONE**|NONE||||NO|NONE|
A12||IOB|IO|UNUSED||1||||||||||
A13||DIFFS|IO_L10N_1/VREF_1|UNUSED||1||||||||||
A14||DIFFS|IO_L01N_1/VRP_1|UNUSED||1||||||||||
A15|||TDO|||||||||||||
@@ -38,72 +38,72 @@ A16|||GND|||||||||||||
B1||DIFFM|IO_L01P_7/VRN_7|UNUSED||7||||||||||
B2|||GND|||||||||||||
B3|||PROG_B|||||||||||||
B4|slideswitch<3>|IOB|IO_L01N_0/VRP_0|INPUT|LVCMOS25|0||||NONE||||NO|NONE|
B5||DIFFM|IO_L25P_0|UNUSED||0||||||||||
B4||DIFFS|IO_L01N_0/VRP_0|UNUSED||0||||||||||
B5|ide_da<0>|IOB|IO_L25P_0|OUTPUT|LVCMOS25|0|12|SLOW|NONE**|||||NO|NONE|
B6||DIFFM|IO_L28P_0|UNUSED||0||||||||||
B7||DIFFM|IO_L30P_0|UNUSED||0||||||||||
B8|sram1_io<14>|IOB|IO_L32N_0/GCLK7|TRISTATE|LVCMOS25|0|12|SLOW|NONE**|||||NO|NONE|
B8||DIFFS|IO_L32N_0/GCLK7|UNUSED||0||||||||||
B9|||GND|||||||||||||
B10|rs232_txd|IOB|IO_L31P_1|OUTPUT|LVCMOS25|1|12|SLOW|NONE**|||||NO|NONE|
B11|sram1_io<1>|IOB|IO_L29N_1|BIDIR|LVCMOS25|1|12|SLOW|NONE**|NONE||||NO|NONE|
B12|sram1_io<10>|IOB|IO_L27N_1|BIDIR|LVCMOS25|1|12|SLOW|NONE**|NONE||||NO|NONE|
B10|sram1_io<15>|IOB|IO_L31P_1|TRISTATE|LVCMOS25|1|12|SLOW|NONE**|||||NO|NONE|
B11|sram1_io<12>|IOB|IO_L29N_1|TRISTATE|LVCMOS25|1|12|SLOW|NONE**|||||NO|NONE|
B12||DIFFS|IO_L27N_1|UNUSED||1||||||||||
B13||DIFFM|IO_L10P_1|UNUSED||1||||||||||
B14||DIFFM|IO_L01P_1/VRN_1|UNUSED||1||||||||||
B15|||GND|||||||||||||
B16||DIFFS|IO_L01N_2/VRP_2|UNUSED||2||||||||||
C1|slideswitch<0>|IOB|IO_L01N_7/VRP_7|INPUT|LVCMOS25|7||||NONE||||NO|NONE|
C2||DIFFS|IO_L16N_7|UNUSED||7||||||||||
C3||DIFFM|IO_L16P_7/VREF_7|UNUSED||7||||||||||
C1||DIFFS|IO_L01N_7/VRP_7|UNUSED||7||||||||||
C2|sram2_io<9>|IOB|IO_L16N_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
C3|sram2_lb_n|IOB|IO_L16P_7/VREF_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
C4|||HSWAP_EN|||||||||||||
C5||DIFFS|IO_L25N_0|UNUSED||0||||||||||
C5|slideswitch<3>|IOB|IO_L25N_0|INPUT|LVCMOS25|0||||NONE||||NO|NONE|
C6||DIFFS|IO_L28N_0|UNUSED||0||||||||||
C7||DIFFS|IO_L30N_0|UNUSED||0||||||||||
C8||DIFFM|IO_L31P_0/VREF_0|UNUSED||0||||||||||
C9|sysclk|IOB|IO_L32N_1/GCLK5|INPUT|LVCMOS25|1||||NONE||||NO|NONE|
C10|sram1_io<6>|IOB|IO|BIDIR|LVCMOS25|1|12|SLOW|NONE**|NONE||||NO|NONE|
C11|sram1_io<2>|IOB|IO_L29P_1|BIDIR|LVCMOS25|1|12|SLOW|NONE**|NONE||||NO|NONE|
C12|sram1_io<5>|IOB|IO_L27P_1|BIDIR|LVCMOS25|1|12|SLOW|NONE**|NONE||||NO|NONE|
C10||IOB|IO|UNUSED||1||||||||||
C11|sram1_io<13>|IOB|IO_L29P_1|TRISTATE|LVCMOS25|1|12|SLOW|NONE**|||||NO|NONE|
C12||DIFFM|IO_L27P_1|UNUSED||1||||||||||
C13|||TMS|||||||||||||
C14|||TCK|||||||||||||
C15||DIFFS|IO_L16N_2|UNUSED||2||||||||||
C16||DIFFM|IO_L01P_2/VRN_2|UNUSED||2||||||||||
D1||DIFFS|IO_L17N_7|UNUSED||7||||||||||
D2||DIFFM|IO_L17P_7|UNUSED||7||||||||||
D3||DIFFM|IO_L19P_7|UNUSED||7||||||||||
D1|sram2_ub_n|IOB|IO_L17N_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
D2|sram2_io<8>|IOB|IO_L17P_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
D3|sram1_ub_n|IOB|IO_L19P_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
D4|||VCCINT||||||||1.2|||||
D5|slideswitch<2>|IOB|IO/VREF_0|INPUT|LVCMOS25|0||||NONE||||NO|NONE|
D6||DIFFM|IO_L27P_0|UNUSED||0||||||||||
D5|slideswitch<0>|IOB|IO/VREF_0|INPUT|LVCMOS25|0||||NONE||||NO|NONE|
D6|slideswitch<2>|IOB|IO_L27P_0|INPUT|LVCMOS25|0||||NONE||||NO|NONE|
D7||DIFFM|IO_L29P_0|UNUSED||0||||||||||
D8|sram1_io<15>|IOB|IO_L31N_0|TRISTATE|LVCMOS25|0|12|SLOW|NONE**|||||NO|NONE|
D9|sram1_io<12>|IOB|IO_L32P_1/GCLK4|TRISTATE|LVCMOS25|1|12|SLOW|NONE**|||||NO|NONE|
D10|sram1_io<7>|IOB|IO_L30N_1|BIDIR|LVCMOS25|1|12|SLOW|NONE**|NONE||||NO|NONE|
D11|sram1_io<11>|IOB|IO_L28N_1|BIDIR|LVCMOS25|1|12|SLOW|NONE**|NONE||||NO|NONE|
D12|sram1_io<9>|IOB|IO/VREF_1|BIDIR|LVCMOS25|1|12|SLOW|NONE**|NONE||||NO|NONE|
D8||DIFFS|IO_L31N_0|UNUSED||0||||||||||
D9|sram_a<17>|IOB|IO_L32P_1/GCLK4|OUTPUT|LVCMOS25|1|12|SLOW|NONE**|||||NO|NONE|
D10||DIFFS|IO_L30N_1|UNUSED||1||||||||||
D11||DIFFS|IO_L28N_1|UNUSED||1||||||||||
D12||IOB|IO/VREF_1|UNUSED||1||||||||||
D13|||VCCINT||||||||1.2|||||
D14||DIFFM|IO_L16P_2|UNUSED||2||||||||||
D15||DIFFS|IO_L17N_2|UNUSED||2||||||||||
D16||DIFFM|IO_L17P_2/VREF_2|UNUSED||2||||||||||
E1||DIFFS|IO_L20N_7|UNUSED||7||||||||||
E2||DIFFM|IO_L20P_7|UNUSED||7||||||||||
E3||DIFFS|IO_L19N_7/VREF_7|UNUSED||7||||||||||
E4|sram2_io<15>|IOB|IO_L21P_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
E1|sram2_io<12>|IOB|IO_L20N_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
E2|sram2_io<10>|IOB|IO_L20P_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
E3|sram2_io<11>|IOB|IO_L19N_7/VREF_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
E4|sram2_io<14>|IOB|IO_L21P_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
E5|||VCCINT||||||||1.2|||||
E6||DIFFS|IO_L27N_0|UNUSED||0||||||||||
E7||DIFFS|IO_L29N_0|UNUSED||0||||||||||
E8|||VCCO_0|||0|||||2.50|||||
E9|||VCCO_1|||1|||||2.50|||||
E10|sram1_io<3>|IOB|IO_L30P_1|BIDIR|LVCMOS25|1|12|SLOW|NONE**|NONE||||NO|NONE|
E11|sram1_io<0>|IOB|IO_L28P_1|BIDIR|LVCMOS25|1|12|SLOW|NONE**|NONE||||NO|NONE|
E10|sram1_io<14>|IOB|IO_L30P_1|TRISTATE|LVCMOS25|1|12|SLOW|NONE**|||||NO|NONE|
E11||DIFFM|IO_L28P_1|UNUSED||1||||||||||
E12|||VCCINT||||||||1.2|||||
E13||DIFFS|IO_L19N_2|UNUSED||2||||||||||
E14||DIFFM|IO_L19P_2|UNUSED||2||||||||||
E15||DIFFS|IO_L20N_2|UNUSED||2||||||||||
E16||DIFFM|IO_L20P_2|UNUSED||2||||||||||
F1|||VCCAUX||||||||2.5|||||
F2|sram_a<16>|IOB|IO_L22N_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
F2|sram2_io<15>|IOB|IO_L22N_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
F3|sram_a<15>|IOB|IO_L22P_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
F4|sram2_io<13>|IOB|IO_L21N_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
F5|sram2_io<12>|IOB|IO_L23P_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
F5||DIFFM|IO_L23P_7|UNUSED||7||||||||||
F6|||GND|||||||||||||
F7|||VCCO_0|||0|||||2.50|||||
F8|||VCCO_0|||0|||||2.50|||||
@@ -112,29 +112,29 @@ F10|||VCCO_1|||1|||||2.50|||||
F11|||GND|||||||||||||
F12||DIFFS|IO_L21N_2|UNUSED||2||||||||||
F13||DIFFM|IO_L21P_2|UNUSED||2||||||||||
F14|sram_a<14>|IOB|IO_L22N_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||||NO|NONE|
F15|sram_a<10>|IOB|IO_L22P_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||||NO|NONE|
F14||DIFFS|IO_L22N_2|UNUSED||2||||||||||
F15||DIFFM|IO_L22P_2|UNUSED||2||||||||||
F16|||VCCAUX||||||||2.5|||||
G1|sram2_io<0>|IOB|IO_L40P_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
G2|button<3>|IOB|IO|INPUT|LVCMOS25|7||||IFD||||YES|NONE|
G3|sram1_lb_n|IOB|IO_L24N_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
G4|sram2_io<14>|IOB|IO_L24P_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
G5|sram1_ce_n|IOB|IO_L23N_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
G1|ide_data_bus<2>|IOB|IO_L40P_7|BIDIR|LVCMOS25|7|12|SLOW|NONE**|IFD||||YES|NONE|
G2|ide_data_bus<7>|IOB|IO|BIDIR|LVCMOS25|7|12|SLOW|NONE**|IFD||||YES|NONE|
G3|ide_diow|IOB|IO_L24N_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
G4|ide_dior|IOB|IO_L24P_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
G5|sram_a<16>|IOB|IO_L23N_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
G6|||VCCO_7|||7|||||2.50|||||
G7|||GND|||||||||||||
G8|||GND|||||||||||||
G9|||GND|||||||||||||
G10|||GND|||||||||||||
G11|||VCCO_2|||2|||||2.50|||||
G12|sram_a<13>|IOB|IO_L23N_2/VREF_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||||NO|NONE|
G13|sram_a<1>|IOB|IO_L23P_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||||NO|NONE|
G14|sram_a<2>|IOB|IO_L24N_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||||NO|NONE|
G15|sram_a<0>|IOB|IO_L24P_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||||NO|NONE|
G16|sram_a<8>|IOB|IO|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||||NO|NONE|
H1||DIFFS|IO_L40N_7/VREF_7|UNUSED||7||||||||||
G12||DIFFS|IO_L23N_2/VREF_2|UNUSED||2||||||||||
G13||DIFFM|IO_L23P_2|UNUSED||2||||||||||
G14||DIFFS|IO_L24N_2|UNUSED||2||||||||||
G15|rs232_txd|IOB|IO_L24P_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||||NO|NONE|
G16||DIFFM|IO|UNUSED||2||||||||||
H1|ide_data_bus<4>|IOB|IO_L40N_7/VREF_7|BIDIR|LVCMOS25|7|12|SLOW|NONE**|IFD||||YES|NONE|
H2|||GND|||||||||||||
H3|sram2_io<5>|IOB|IO_L39N_7|OUTPUT|LVCMOS25|7|12|SLOW|NONE**|||||NO|NONE|
H4||DIFFM|IO_L39P_7|UNUSED||7||||||||||
H3|ide_data_bus<5>|IOB|IO_L39N_7|BIDIR|LVCMOS25|7|12|SLOW|NONE**|IFD||||YES|NONE|
H4|button<3>|IOB|IO_L39P_7|INPUT|LVCMOS25|7||||IFD||||YES|NONE|
H5|||VCCO_7|||7|||||2.50|||||
H6|||VCCO_7|||7|||||2.50|||||
H7|||GND|||||||||||||
@@ -143,14 +143,14 @@ H9|||GND|||||||||||||
H10|||GND|||||||||||||
H11|||VCCO_2|||2|||||2.50|||||
H12|||VCCO_2|||2|||||2.50|||||
H13|sram_a<9>|IOB|IO_L39N_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||||NO|NONE|
H14|sram_a<3>|IOB|IO_L39P_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||||NO|NONE|
H15|sram_a<4>|IOB|IO_L40N_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||||NO|NONE|
H16|sram_a<6>|IOB|IO_L40P_2/VREF_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||||NO|NONE|
J1|sram_a<17>|IOB|IO_L40P_6/VREF_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
J2||DIFFS|IO_L40N_6|UNUSED||6||||||||||
J3|ide_data_bus<15>|IOB|IO_L39P_6|TRISTATE|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
J4|ide_data_bus<13>|IOB|IO_L39N_6|TRISTATE|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
H13||DIFFS|IO_L39N_2|UNUSED||2||||||||||
H14|sram_oe_n|IOB|IO_L39P_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||||NO|NONE|
H15|sram_we_n|IOB|IO_L40N_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||||NO|NONE|
H16|sram_a<7>|IOB|IO_L40P_2/VREF_2|OUTPUT|LVCMOS25|2|12|SLOW|NONE**|||||NO|NONE|
J1|ide_data_bus<0>|IOB|IO_L40P_6/VREF_6|BIDIR|LVCMOS25|6|12|SLOW|NONE**|IFD||||YES|NONE|
J2|ide_data_bus<3>|IOB|IO_L40N_6|BIDIR|LVCMOS25|6|12|SLOW|NONE**|IFD||||YES|NONE|
J3|ide_data_bus<10>|IOB|IO_L39P_6|BIDIR|LVCMOS25|6|12|SLOW|NONE**|IFD||||YES|NONE|
J4|ide_data_bus<1>|IOB|IO_L39N_6|BIDIR|LVCMOS25|6|12|SLOW|NONE**|IFD||||YES|NONE|
J5|||VCCO_6|||6|||||2.50|||||
J6|||VCCO_6|||6|||||2.50|||||
J7|||GND|||||||||||||
@@ -159,84 +159,84 @@ J9|||GND|||||||||||||
J10|||GND|||||||||||||
J11|||VCCO_3|||3|||||2.50|||||
J12|||VCCO_3|||3|||||2.50|||||
J13|sram_a<5>|IOB|IO_L39P_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
J14|sram_a<7>|IOB|IO_L39N_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
J13|sram1_io<3>|IOB|IO_L39P_3|BIDIR|LVCMOS25|3|12|SLOW|NONE**|NONE||||NO|NONE|
J14|sram1_io<4>|IOB|IO_L39N_3|BIDIR|LVCMOS25|3|12|SLOW|NONE**|NONE||||NO|NONE|
J15|||GND|||||||||||||
J16|sram_a<12>|IOB|IO_L40N_3/VREF_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
K1|sram2_io<7>|IOB|IO|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
K2||DIFFM|IO_L24P_6|UNUSED||6||||||||||
K3||DIFFS|IO_L24N_6/VREF_6|UNUSED||6||||||||||
K4||DIFFM|IO_L23P_6|UNUSED||6||||||||||
K5||DIFFS|IO_L23N_6|UNUSED||6||||||||||
J16|sram_a<0>|IOB|IO_L40N_3/VREF_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
K1|ide_data_bus<11>|IOB|IO|BIDIR|LVCMOS25|6|12|SLOW|NONE**|IFD||||YES|NONE|
K2|ide_data_bus<9>|IOB|IO_L24P_6|BIDIR|LVCMOS25|6|12|SLOW|NONE**|IFD||||YES|NONE|
K3|ide_data_bus<8>|IOB|IO_L24N_6/VREF_6|BIDIR|LVCMOS25|6|12|SLOW|NONE**|IFD||||YES|NONE|
K4|ide_cs<0>|IOB|IO_L23P_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
K5|ide_data_bus<6>|IOB|IO_L23N_6|BIDIR|LVCMOS25|6|12|SLOW|NONE**|IFD||||YES|NONE|
K6|||VCCO_6|||6|||||2.50|||||
K7|||GND|||||||||||||
K8|||GND|||||||||||||
K9|||GND|||||||||||||
K10|||GND|||||||||||||
K11|||VCCO_3|||3|||||2.50|||||
K12||DIFFS|IO_L23N_3|UNUSED||3||||||||||
K13||DIFFM|IO_L24P_3|UNUSED||3||||||||||
K14||DIFFS|IO_L24N_3|UNUSED||3||||||||||
K15|sram_we_n|IOB|IO|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
K16|sram_a<11>|IOB|IO_L40P_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
K12|sram_a<13>|IOB|IO_L23N_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
K13|sram1_io<6>|IOB|IO_L24P_3|BIDIR|LVCMOS25|3|12|SLOW|NONE**|NONE||||NO|NONE|
K14|sram_a<14>|IOB|IO_L24N_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
K15|sram1_io<5>|IOB|IO|BIDIR|LVCMOS25|3|12|SLOW|NONE**|NONE||||NO|NONE|
K16|sram_a<3>|IOB|IO_L40P_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
L1|||VCCAUX||||||||2.5|||||
L2|sram2_io<11>|IOB|IO_L22P_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
L3|sram2_io<10>|IOB|IO_L22N_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
L4|sram2_ub_n|IOB|IO_L21P_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
L5|sram1_ub_n|IOB|IO_L21N_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
L2|ide_data_bus<12>|IOB|IO_L22P_6|TRISTATE|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
L3|ide_data_bus<14>|IOB|IO_L22N_6|TRISTATE|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
L4|ide_data_bus<15>|IOB|IO_L21P_6|TRISTATE|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
L5|ide_data_bus<13>|IOB|IO_L21N_6|TRISTATE|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
L6|||GND|||||||||||||
L7|||VCCO_5|||5|||||2.50|||||
L8|||VCCO_5|||5|||||2.50|||||
L9|||VCCO_4|||4|||||2.50|||||
L10|||VCCO_4|||4|||||2.50|||||
L11|||GND|||||||||||||
L12||DIFFM|IO_L23P_3/VREF_3|UNUSED||3||||||||||
L13||DIFFS|IO_L21N_3|UNUSED||3||||||||||
L14||DIFFM|IO_L22P_3|UNUSED||3||||||||||
L15||DIFFS|IO_L22N_3|UNUSED||3||||||||||
L12|sram_a<10>|IOB|IO_L23P_3/VREF_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
L13|sram_a<11>|IOB|IO_L21N_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
L14|sram_a<9>|IOB|IO_L22P_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
L15|sram_a<8>|IOB|IO_L22N_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
L16|||VCCAUX||||||||2.5|||||
M1|sram2_io<9>|IOB|IO_L20P_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
M2|sram2_io<8>|IOB|IO_L20N_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
M3|sram2_io<6>|IOB|IO_L19P_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
M4|sram2_lb_n|IOB|IO_L19N_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
M1|sram2_io<6>|IOB|IO_L20P_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
M2|sram2_io<5>|IOB|IO_L20N_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
M3|sram2_io<4>|IOB|IO_L19P_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
M4|sram2_io<3>|IOB|IO_L19N_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
M5|||VCCINT||||||||1.2|||||
M6||DIFFM|IO_L28P_5/D7|UNUSED||5||||||||||
M7|ide_data_bus<4>|IOB|IO_L30P_5|BIDIR|LVCMOS25|5|12|SLOW|NONE**|IFD||||YES|NONE|
M7||DIFFM|IO_L30P_5|UNUSED||5||||||||||
M8|||VCCO_5|||5|||||2.50|||||
M9|||VCCO_4|||4|||||2.50|||||
M10||DIFFS|IO_L29N_4|UNUSED||4||||||||||
M11||DIFFS|IO_L27N_4/DIN/D0|UNUSED||4||||||||||
M11|sram_a<2>|IOB|IO_L27N_4/DIN/D0|OUTPUT|LVCMOS25|4|12|SLOW|NONE**|||||NO|NONE|
M12|||VCCINT||||||||1.2|||||
M13||DIFFM|IO_L21P_3|UNUSED||3||||||||||
M13|sram_a<5>|IOB|IO_L21P_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
M14||DIFFS|IO_L19N_3|UNUSED||3||||||||||
M15||DIFFM|IO_L20P_3|UNUSED||3||||||||||
M16||DIFFS|IO_L20N_3|UNUSED||3||||||||||
N1|sram2_io<4>|IOB|IO_L17P_6/VREF_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
N2|sram2_io<3>|IOB|IO_L17N_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
N3|sram2_io<2>|IOB|IO_L16P_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
M15|sram_a<12>|IOB|IO_L20P_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
M16|sram_a<6>|IOB|IO_L20N_3|OUTPUT|LVCMOS25|3|12|SLOW|NONE**|||||NO|NONE|
N1|sram2_io<2>|IOB|IO_L17P_6/VREF_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
N2|sram2_io<1>|IOB|IO_L17N_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
N3|sram2_io<0>|IOB|IO_L16P_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
N4|||VCCINT||||||||1.2|||||
N5||IOB|IO|UNUSED||5||||||||||
N6||DIFFS|IO_L28N_5/D6|UNUSED||5||||||||||
N7|ide_data_bus<6>|IOB|IO_L30N_5|BIDIR|LVCMOS25|5|12|SLOW|NONE**|IFD||||YES|NONE|
N8|ide_da<2>|IOB|IO_L32P_5/GCLK2|OUTPUT|LVCMOS25|5|12|SLOW|NONE**|||||NO|NONE|
N9|ide_data_bus<5>|IOB|IO_L31N_4/INIT_B|BIDIR|LVCMOS25|4|12|SLOW|NONE**|IFD||||YES|NONE|
N10|ide_data_bus<10>|IOB|IO_L29P_4|BIDIR|LVCMOS25|4|12|SLOW|NONE**|IFD||||YES|NONE|
N11||DIFFM|IO_L27P_4/D1|UNUSED||4||||||||||
N12||IOB|IO/VREF_4|UNUSED||4||||||||||
N7||DIFFS|IO_L30N_5|UNUSED||5||||||||||
N8|sram1_io<0>|IOB|IO_L32P_5/GCLK2|BIDIR|LVCMOS25|5|12|SLOW|NONE**|NONE||||NO|NONE|
N9|sram1_io<8>|IOB|IO_L31N_4/INIT_B|BIDIR|LVCMOS25|4|12|SLOW|NONE**|NONE||||NO|NONE|
N10||DIFFM|IO_L29P_4|UNUSED||4||||||||||
N11|rs232_rxd|IOB|IO_L27P_4/D1|INPUT|LVCMOS25|4||||IFD||||YES|NONE|
N12|sram1_io<9>|IOB|IO/VREF_4|BIDIR|LVCMOS25|4|12|SLOW|NONE**|NONE||||NO|NONE|
N13|||VCCINT||||||||1.2|||||
N14||DIFFM|IO_L19P_3|UNUSED||3||||||||||
N15||DIFFM|IO_L17P_3/VREF_3|UNUSED||3||||||||||
N16||DIFFS|IO_L17N_3|UNUSED||3||||||||||
P1|sram2_ce_n|IOB|IO_L01P_6/VRN_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
P2|sram2_io<1>|IOB|IO_L16N_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
P2|sram1_lb_n|IOB|IO_L16N_6|OUTPUT|LVCMOS25|6|12|SLOW|NONE**|||||NO|NONE|
P3|||M0|||||||||||||
P4|||M2|||||||||||||
P5|ide_dior|IOB|IO_L27P_5|OUTPUT|LVCMOS25|5|12|SLOW|NONE**|||||NO|NONE|
P6|ide_data_bus<7>|IOB|IO_L29P_5/VREF_5|BIDIR|LVCMOS25|5|12|SLOW|NONE**|IFD||||YES|NONE|
P5|ide_cs<1>|IOB|IO_L27P_5|OUTPUT|LVCMOS25|5|12|SLOW|NONE**|||||NO|NONE|
P6||DIFFM|IO_L29P_5/VREF_5|UNUSED||5||||||||||
P7||IOB|IO|UNUSED||5||||||||||
P8|ide_da<1>|IOB|IO_L32N_5/GCLK3|OUTPUT|LVCMOS25|5|12|SLOW|NONE**|||||NO|NONE|
P9|ide_da<0>|IOB|IO_L31P_4/DOUT/BUSY|OUTPUT|LVCMOS25|4|12|SLOW|NONE**|||||NO|NONE|
P10|ide_data_bus<2>|IOB|IO_L30N_4/D2|BIDIR|LVCMOS25|4|12|SLOW|NONE**|IFD||||YES|NONE|
P8|sram1_io<1>|IOB|IO_L32N_5/GCLK3|BIDIR|LVCMOS25|5|12|SLOW|NONE**|NONE||||NO|NONE|
P9|sram_a<4>|IOB|IO_L31P_4/DOUT/BUSY|OUTPUT|LVCMOS25|4|12|SLOW|NONE**|||||NO|NONE|
P10||DIFFS|IO_L30N_4/D2|UNUSED||4||||||||||
P11||DIFFS|IO_L28N_4|UNUSED||4||||||||||
P12||DIFFS|IO_L25N_4|UNUSED||4||||||||||
P13||IOB|IO/VREF_4|UNUSED||4||||||||||
@@ -245,14 +245,14 @@ P15||DIFFS|IO_L16N_3|UNUSED||3||||||||||
P16||DIFFS|IO_L01N_3/VRP_3|UNUSED||3||||||||||
R1||DIFFS|IO_L01N_6/VRP_6|UNUSED||6||||||||||
R2|||GND|||||||||||||
R3|ide_data_bus<12>|IOB|IO_L01P_5/CS_B|TRISTATE|LVCMOS25|5|12|SLOW|NONE**|||||NO|NONE|
R4||DIFFM|IO_L10P_5/VRN_5|UNUSED||5||||||||||
R5|ide_diow|IOB|IO_L27N_5/VREF_5|OUTPUT|LVCMOS25|5|12|SLOW|NONE**|||||NO|NONE|
R6|ide_data_bus<3>|IOB|IO_L29N_5|BIDIR|LVCMOS25|5|12|SLOW|NONE**|IFD||||YES|NONE|
R7|ide_data_bus<11>|IOB|IO_L31P_5/D5|BIDIR|LVCMOS25|5|12|SLOW|NONE**|IFD||||YES|NONE|
R3||DIFFM|IO_L01P_5/CS_B|UNUSED||5||||||||||
R4|sram2_io<7>|IOB|IO_L10P_5/VRN_5|OUTPUT|LVCMOS25|5|12|SLOW|NONE**|||||NO|NONE|
R5|ide_da<1>|IOB|IO_L27N_5/VREF_5|OUTPUT|LVCMOS25|5|12|SLOW|NONE**|||||NO|NONE|
R6||DIFFS|IO_L29N_5|UNUSED||5||||||||||
R7||DIFFM|IO_L31P_5/D5|UNUSED||5||||||||||
R8|||GND|||||||||||||
R9|ide_data_bus<9>|IOB|IO_L32N_4/GCLK1|BIDIR|LVCMOS25|4|12|SLOW|NONE**|IFD||||YES|NONE|
R10|ide_data_bus<1>|IOB|IO_L30P_4/D3|BIDIR|LVCMOS25|4|12|SLOW|NONE**|IFD||||YES|NONE|
R9|sram1_io<11>|IOB|IO_L32N_4/GCLK1|BIDIR|LVCMOS25|4|12|SLOW|NONE**|NONE||||NO|NONE|
R10||DIFFM|IO_L30P_4/D3|UNUSED||4||||||||||
R11||DIFFM|IO_L28P_4|UNUSED||4||||||||||
R12||DIFFM|IO_L25P_4|UNUSED||4||||||||||
R13||DIFFS|IO_L01N_4/VRP_4|UNUSED||4||||||||||
@@ -261,18 +261,18 @@ R15|||GND|||||||||||||
R16||DIFFM|IO_L01P_3/VRN_3|UNUSED||3||||||||||
T1|||GND|||||||||||||
T2|||M1|||||||||||||
T3|ide_data_bus<14>|IOB|IO_L01N_5/RDWR_B|TRISTATE|LVCMOS25|5|12|SLOW|NONE**|||||NO|NONE|
T3||DIFFS|IO_L01N_5/RDWR_B|UNUSED||5||||||||||
T4||DIFFS|IO_L10N_5/VRP_5|UNUSED||5||||||||||
T5||IOB|IO|UNUSED||5||||||||||
T5|ide_da<2>|IOB|IO|OUTPUT|LVCMOS25|5|12|SLOW|NONE**|||||NO|NONE|
T6|||VCCAUX||||||||2.5|||||
T7|ide_cs<1>|IOB|IO_L31N_5/D4|OUTPUT|LVCMOS25|5|12|SLOW|NONE**|||||NO|NONE|
T8|ide_cs<0>|IOB|IO/VREF_5|OUTPUT|LVCMOS25|5|12|SLOW|NONE**|||||NO|NONE|
T9|ide_data_bus<8>|IOB|IO_L32P_4/GCLK0|BIDIR|LVCMOS25|4|12|SLOW|NONE**|IFD||||YES|NONE|
T10|ide_data_bus<0>|IOB|IO/VREF_4|BIDIR|LVCMOS25|4|12|SLOW|NONE**|IFD||||YES|NONE|
T7||DIFFS|IO_L31N_5/D4|UNUSED||5||||||||||
T8|sram1_io<2>|IOB|IO/VREF_5|BIDIR|LVCMOS25|5|12|SLOW|NONE**|NONE||||NO|NONE|
T9|sram1_io<7>|IOB|IO_L32P_4/GCLK0|BIDIR|LVCMOS25|4|12|SLOW|NONE**|NONE||||NO|NONE|
T10|sram1_ce_n|IOB|IO/VREF_4|OUTPUT|LVCMOS25|4|12|SLOW|NONE**|||||NO|NONE|
T11|||VCCAUX||||||||2.5|||||
T12||IOB|IO|UNUSED||4||||||||||
T12|sram_a<1>|IOB|IO|OUTPUT|LVCMOS25|4|12|SLOW|NONE**|||||NO|NONE|
T13||DIFFM|IO_L01P_4/VRN_4|UNUSED||4||||||||||
T14|rs232_rxd|IOB|IO|INPUT|LVCMOS25|4||||IFD||||YES|NONE|
T14|sram1_io<10>|IOB|IO|BIDIR|LVCMOS25|4|12|SLOW|NONE**|NONE||||NO|NONE|
T15|||CCLK|||||||||||||
T16|||GND|||||||||||||

100
xilinx/pdp8/top.par
View File

@@ -1,7 +1,7 @@
Release 8.2i par I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
wide:: Wed Apr 14 19:03:38 2010
wide:: Fri Apr 16 08:16:15 2010
par -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd top.pcf
@@ -28,7 +28,7 @@ Device Utilization Summary:
Number of External IOBs 89 out of 173 51%
Number of LOCed IOBs 0 out of 89 0%
Number of Slices 1045 out of 7680 13%
Number of Slices 1135 out of 7680 14%
Number of SLICEMs 96 out of 3840 2%
@@ -42,7 +42,7 @@ Router effort level (-rl): Standard
Starting Placer
Phase 1.1
Phase 1.1 (Checksum:98c64f) REAL time: 7 secs
Phase 1.1 (Checksum:98cab7) REAL time: 7 secs
Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 7 secs
@@ -51,58 +51,64 @@ Phase 3.2
.
Phase 3.2 (Checksum:1c9c37d) REAL time: 11 secs
Phase 3.2 (Checksum:1c9c37d) REAL time: 12 secs
Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 11 secs
Phase 4.3 (Checksum:26259fc) REAL time: 12 secs
Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 11 secs
Phase 5.5 (Checksum:2faf07b) REAL time: 12 secs
Phase 6.8
.........
.........
.............
........
.................................
........
...............................
.....
Phase 6.8 (Checksum:c43eff) REAL time: 28 secs
.....
Phase 6.8 (Checksum:c1aa4b) REAL time: 30 secs
Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 28 secs
Phase 7.5 (Checksum:42c1d79) REAL time: 30 secs
Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 47 secs
Phase 8.18 (Checksum:4c4b3f8) REAL time: 51 secs
Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 47 secs
Phase 9.5 (Checksum:55d4a77) REAL time: 51 secs
Writing design to file top.ncd
Total REAL time to Placer completion: 49 secs
Total CPU time to Placer completion: 49 secs
Total REAL time to Placer completion: 54 secs
Total CPU time to Placer completion: 54 secs
Starting Router
Phase 1: 7815 unrouted; REAL time: 49 secs
Phase 1: 8419 unrouted; REAL time: 54 secs
Phase 2: 7293 unrouted; REAL time: 51 secs
Phase 2: 7883 unrouted; REAL time: 55 secs
Phase 3: 1774 unrouted; REAL time: 52 secs
Phase 3: 1987 unrouted; REAL time: 57 secs
Phase 4: 1774 unrouted; (40393) REAL time: 53 secs
Phase 4: 1987 unrouted; (77716) REAL time: 58 secs
Phase 5: 1822 unrouted; (0) REAL time: 54 secs
Phase 5: 2030 unrouted; (0) REAL time: 59 secs
Phase 6: 0 unrouted; (0) REAL time: 59 secs
Phase 6: 0 unrouted; (229) REAL time: 1 mins 5 secs
Phase 7: 0 unrouted; (0) REAL time: 1 mins 1 secs
Phase 7: 0 unrouted; (229) REAL time: 1 mins 6 secs
Phase 8: 0 unrouted; (204) REAL time: 1 mins 12 secs
Phase 9: 0 unrouted; (121) REAL time: 1 mins 20 secs
Phase 10: 0 unrouted; (121) REAL time: 1 mins 21 secs
WARNING:Route:447 - CLK Net:io/tt/baud_rate_generator/tx_baud_clk may have excessive skew because
2 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:io/kw/kw_src_clk may have excessive skew because
6 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:io/tt/baud_rate_generator/tx_baud_clk may have excessive skew because
1 NON-CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:io/tt/baud_rate_generator/rx_baud_clk may have excessive skew because
1 NON-CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:reset_sw/slowclk may have excessive skew because
@@ -110,8 +116,8 @@ WARNING:Route:447 - CLK Net:reset_sw/slowclk may have excessive skew because
WARNING:Route:447 - CLK Net:clk may have excessive skew because
1 NON-CLK pins failed to route using a CLK template.
Total REAL time to Router completion: 1 mins 1 secs
Total CPU time to Router completion: 1 mins 1 secs
Total REAL time to Router completion: 1 mins 21 secs
Total CPU time to Router completion: 1 mins 21 secs
Partition Implementation Status
-------------------------------
@@ -129,19 +135,19 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk | BUFGMUX7| No | 429 | 0.390 | 1.006 |
+---------------------+--------------+------+------+------------+-------------+
| sysclk_BUFGP | BUFGMUX5| No | 23 | 0.126 | 0.737 |
| sysclk_BUFGP | BUFGMUX5| No | 23 | 0.107 | 0.729 |
+---------------------+--------------+------+------+------------+-------------+
|io/tt/baud_rate_gene | | | | | |
| rator/rx_baud_clk | BUFGMUX1| No | 24 | 0.182 | 0.841 |
| rator/rx_baud_clk | BUFGMUX1| No | 24 | 0.208 | 0.861 |
+---------------------+--------------+------+------+------------+-------------+
| io/kw/kw_src_clk | Local| | 7 | 0.601 | 1.529 |
| clk | BUFGMUX7| No | 445 | 0.402 | 1.013 |
+---------------------+--------------+------+------+------------+-------------+
| reset_sw/slowclk | Local| | 8 | 0.242 | 2.907 |
| io/kw/kw_src_clk | Local| | 7 | 0.334 | 1.254 |
+---------------------+--------------+------+------+------------+-------------+
| reset_sw/slowclk | Local| | 8 | 0.475 | 3.214 |
+---------------------+--------------+------+------+------------+-------------+
|io/tt/baud_rate_gene | | | | | |
| rator/tx_baud_clk | Local| | 10 | 0.038 | 2.019 |
| rator/tx_baud_clk | Local| | 10 | 1.260 | 2.212 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
@@ -155,15 +161,15 @@ the minimum and maximum path delays which includes logic delays.
The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
The AVERAGE CONNECTION DELAY for this design is: 1.201
The MAXIMUM PIN DELAY IS: 5.419
The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 4.145
The AVERAGE CONNECTION DELAY for this design is: 1.193
The MAXIMUM PIN DELAY IS: 6.943
The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 5.121
Listing Pin Delays by value: (nsec)
d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 6.00 d >= 6.00
d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 7.00 d >= 7.00
--------- --------- --------- --------- --------- ---------
3887 2667 988 229 7 0
4218 2975 763 395 31 0
Timing Score: 0
@@ -174,21 +180,21 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Requested | Actual | Logic | Absolute |Number of
| | | Levels | Slack |errors
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | N/A | 11.175ns | 7 | N/A | N/A
Autotimespec constraint for clock net clk | N/A | 11.634ns | 8 | N/A | N/A
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net io/ | N/A | 3.775ns | 3 | N/A | N/A
Autotimespec constraint for clock net io/ | N/A | 3.636ns | 3 | N/A | N/A
kw/kw_src_clk | | | | |
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net sys | N/A | 4.365ns | 2 | N/A | N/A
Autotimespec constraint for clock net sys | N/A | 4.081ns | 13 | N/A | N/A
clk_BUFGP | | | | |
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net io/ | N/A | 5.099ns | 3 | N/A | N/A
Autotimespec constraint for clock net io/ | N/A | 5.078ns | 3 | N/A | N/A
tt/baud_rate_generator/rx_baud_clk | | | | |
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net res | N/A | 3.096ns | 0 | N/A | N/A
Autotimespec constraint for clock net res | N/A | 2.808ns | 0 | N/A | N/A
et_sw/slowclk | | | | |
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net io/ | N/A | 3.583ns | 3 | N/A | N/A
Autotimespec constraint for clock net io/ | N/A | 4.548ns | 1 | N/A | N/A
tt/baud_rate_generator/tx_baud_clk | | | | |
------------------------------------------------------------------------------------------------------
@@ -202,10 +208,10 @@ Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 1 mins 6 secs
Total CPU time to PAR completion: 1 mins 6 secs
Total REAL time to PAR completion: 1 mins 25 secs
Total CPU time to PAR completion: 1 mins 25 secs
Peak Memory Usage: 414 MB
Peak Memory Usage: 427 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.

2
xilinx/pdp8/top.pcf
View File

@@ -1,5 +1,5 @@
//! **************************************************************************
// Written by: Map I.31 on Wed Apr 14 19:03:33 2010
// Written by: Map I.31 on Fri Apr 16 08:16:08 2010
//! **************************************************************************
SCHEMATIC START;

466
xilinx/pdp8/top.syr
View File

@@ -2,11 +2,11 @@ Release 8.2i - xst I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.09 s | Elapsed : 0.00 / 0.00 s
CPU : 0.00 / 0.08 s | Elapsed : 0.00 / 0.00 s
-->
Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.09 s | Elapsed : 0.00 / 0.00 s
CPU : 0.00 / 0.08 s | Elapsed : 0.00 / 0.00 s
-->
Reading design: top.prj
@@ -137,59 +137,37 @@ Analyzing hierarchy for module <top> in library <work>.
Analyzing hierarchy for module <debounce> in library <work>.
Analyzing hierarchy for module <pdp8> in library <work> with parameters.
E3 = "1011"
E2 = "1010"
E1 = "1001"
E0 = "1000"
F1 = "0001"
F0 = "0000"
E3 = "1011"
D2 = "0110"
D1 = "0101"
D0 = "0100"
F2 = "0010"
E0 = "1000"
D3 = "0111"
D2 = "0110"
H0 = "1100"
F3 = "0011"
F2 = "0010"
Analyzing hierarchy for module <pdp8_io> in library <work>.
Analyzing hierarchy for module <pdp8_ram> in library <work>.
Analyzing hierarchy for module <pdp8_kw> in library <work> with parameters.
F2 = "0010"
F1 = "0001"
F0 = "0000"
F3 = "0011"
F2 = "0010"
Analyzing hierarchy for module <pdp8_tt> in library <work> with parameters.
F0 = "0000"
F2 = "0010"
F3 = "0011"
F1 = "0001"
F3 = "0011"
F2 = "0010"
Analyzing hierarchy for module <pdp8_rf> in library <work> with parameters.
DB_next_xfer_read = "0101"
DB_next_xfer_incr = "0110"
DB_idle = "0000"
DB_start_xfer2 = "0010"
DB_start_xfer1 = "0001"
DB_read_new_page = "1101"
DRE_bit = "010000000000"
DB_write_old_page = "1111"
DB_start_xfer3 = "0011"
F0 = "0000"
EIE_bit = "000100000000"
DRL_bit = "000000000100"
F3 = "0011"
F2 = "0010"
F1 = "0001"
PCA_bit = "100000000000"
NXD_bit = "000000000010"
MEX_bit = "000000111000"
WC_ADDR = "000111111101000"
PIE_bit = "000010000000"
PER_bit = "000000000001"
WLS_bit = "001000000000"
DB_begin_xfer_write = "0111"
CIE_bit = "000001000000"
CA_ADDR = "000111111101001"
@@ -199,6 +177,28 @@ Analyzing hierarchy for module <pdp8_rf> in library <work> with parameters.
DB_done_xfer3 = "1100"
DB_done_xfer2 = "1011"
DB_done_xfer1 = "1010"
DB_next_xfer_read = "0101"
DB_next_xfer_incr = "0110"
DB_idle = "0000"
DB_read_new_page = "1101"
DB_start_xfer1 = "0001"
DB_write_old_page = "1110"
DB_start_xfer3 = "0011"
DB_start_xfer2 = "0010"
DRE_bit = "010000000000"
DRL_bit = "000000000100"
F1 = "0001"
F0 = "0000"
EIE_bit = "000100000000"
MEX_bit = "000000111000"
F3 = "0011"
F2 = "0010"
PER_bit = "000000000001"
PCA_bit = "100000000000"
NXD_bit = "000000000010"
WLS_bit = "001000000000"
WC_ADDR = "000111111101000"
PIE_bit = "000010000000"
Analyzing hierarchy for module <brg> in library <work> with parameters.
SYS_CLK = "10111110101111000010000000"
@@ -211,51 +211,51 @@ Analyzing hierarchy for module <uart> in library <work>.
Analyzing hierarchy for module <ram_256x12> in library <work>.
Analyzing hierarchy for module <ide_disk> in library <work> with parameters.
IDE_STATUS_IDX = "00000000000000000000000000000001"
ATA_FEATURE = "10001"
ATA_ALTER = "01110"
ATA_COMMAND = "10111"
ATA_CMD_WRITE = "0000000000110000"
ATA_CMD_READ = "0000000000100000"
ATA_DATA = "10000"
ATA_CYLLOW = "10100"
ATA_CYLHIGH = "10101"
ATA_COMMAND = "10111"
ATA_DEVCTRL = "01110"
ATA_DATA = "10000"
ATA_FEATURE = "10001"
ATA_ERROR = "10001"
ATA_DRVHEAD = "10110"
ATA_SECNUM = "10011"
ATA_DEVCTRL = "01110"
ATA_SECCNT = "10010"
IDE_STATUS_CORR = "00000000000000000000000000000010"
IDE_STATUS_BSY = "00000000000000000000000000000111"
ATA_STATUS = "10111"
ATA_SECNUM = "10011"
IDE_STATUS_DRQ = "00000000000000000000000000000011"
IDE_STATUS_DRDY = "00000000000000000000000000000110"
IDE_STATUS_CORR = "00000000000000000000000000000010"
IDE_STATUS_ERR = "00000000000000000000000000000000"
IDE_STATUS_DWF = "00000000000000000000000000000101"
IDE_STATUS_DSC = "00000000000000000000000000000100"
init1 = "00010"
init0 = "00001"
IDE_STATUS_IDX = "00000000000000000000000000000001"
init2 = "00011"
init11 = "01100"
init10 = "01011"
init1 = "00010"
init3 = "00100"
init2 = "00011"
init6 = "00111"
init5 = "00110"
init4 = "00101"
init3 = "00100"
init8 = "01001"
init7 = "01000"
init6 = "00111"
last1 = "10010"
last0 = "10001"
init9 = "01010"
read0 = "01101"
last3 = "10100"
last2 = "10011"
wait0 = "10101"
ready = "00000"
read1 = "01110"
read0 = "01101"
wait1 = "10110"
wait0 = "10101"
write1 = "10000"
write0 = "01111"
wait1 = "10110"
Analyzing hierarchy for module <ide> in library <work> with parameters.
idle = "000"
@@ -350,7 +350,7 @@ Analyzing module <pdp8_rf> in library <work>.
DB_done_xfer2 = 4'b1011
DB_done_xfer3 = 4'b1100
DB_read_new_page = 4'b1101
DB_write_old_page = 4'b1111
DB_write_old_page = 4'b1110
Module <pdp8_rf> is correct for synthesis.
Analyzing module <ram_256x12> in library <work>.
@@ -706,7 +706,6 @@ Unit <ide_disk> synthesized.
Synthesizing Unit <pdp8_rf>.
Related source file is "../../rtl/pdp8_rf.v".
WARNING:Xst:647 - Input <mb<11:3>> is never used.
WARNING:Xst:646 - Signal <db_done> is assigned but never used.
WARNING:Xst:646 - Signal <ide_error> is assigned but never used.
WARNING:Xst:646 - Signal <PEF> is assigned but never used.
WARNING:Xst:646 - Signal <buffer_rd> is assigned but never used.
@@ -714,9 +713,9 @@ WARNING:Xst:646 - Signal <active> is assigned but never used.
Found finite state machine <FSM_6> for signal <db_state>.
-----------------------------------------------------------------------
| States | 15 |
| Transitions | 33 |
| Transitions | 34 |
| Inputs | 8 |
| Outputs | 12 |
| Outputs | 11 |
| Clock | clk (rising_edge) |
| Reset | reset (positive) |
| Reset type | synchronous |
@@ -724,22 +723,27 @@ WARNING:Xst:646 - Signal <active> is assigned but never used.
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 4x1-bit ROM for signal <$mux0018> created at line 594.
Found 4x2-bit ROM for signal <$rom0000>.
Found 4x1-bit ROM for signal <set_db_done>.
Found 4x1-bit ROM for signal <load_buffer_hold>.
Found 4x1-bit ROM for signal <set_buffer_dirty>.
Found 4x1-bit ROM for signal <$mux0029> created at line 622.
Found 1-bit 4-to-1 multiplexer for signal <io_clear_ac>.
Found 12-bit 4-to-1 multiplexer for signal <io_data_out>.
Found 1-bit 4-to-1 multiplexer for signal <io_skip>.
Found 12-bit adder for signal <$add0001> created at line 885.
Found 12-bit adder for signal <$addsub0000> created at line 906.
Found 15-bit adder for signal <$addsub0001> created at line 905.
Found 20-bit adder for signal <$addsub0002> created at line 904.
Found 1-bit 4-to-1 multiplexer for signal <$mux0015>.
Found 1-bit 4-to-1 multiplexer for signal <$mux0016>.
Found 12-bit adder for signal <$add0001> created at line 977.
Found 12-bit adder for signal <$add0002> created at line 959.
Found 12-bit adder for signal <$addsub0000> created at line 978.
Found 1-bit 4-to-1 multiplexer for signal <$mux0026>.
Found 1-bit 4-to-1 multiplexer for signal <$mux0027>.
Found 1-bit register for signal <buffer_dirty>.
Found 12-bit register for signal <buffer_disk_addr>.
Found 12-bit register for signal <buffer_hold>.
Found 12-bit comparator equal for signal <buffer_matches_DMA>.
Found 1-bit register for signal <CIE>.
Found 1-bit register for signal <db_done>.
Found 1-bit register for signal <DCF>.
Found 20-bit register for signal <disk_addr>.
Found 20-bit up counter for signal <disk_addr>.
Found 12-bit register for signal <DMA>.
Found 15-bit register for signal <dma_addr>.
Found 12-bit register for signal <dma_wc>.
@@ -747,25 +751,27 @@ WARNING:Xst:646 - Signal <active> is assigned but never used.
Found 8-bit register for signal <EMA>.
Found 1-bit register for signal <is_read>.
Found 3-bit register for signal <MEX>.
Found 11-bit up counter for signal <photocell_counter>.
Found 8-bit comparator less for signal <PCA>.
Found 8-bit up counter for signal <photocell_counter>.
Found 1-bit register for signal <PIE>.
Summary:
inferred 1 Finite State Machine(s).
inferred 1 ROM(s).
inferred 1 Counter(s).
inferred 100 D-type flip-flop(s).
inferred 4 Adder/Subtractor(s).
inferred 1 Comparator(s).
inferred 15 Multiplexer(s).
inferred 5 ROM(s).
inferred 2 Counter(s).
inferred 81 D-type flip-flop(s).
inferred 3 Adder/Subtractor(s).
inferred 2 Comparator(s).
inferred 16 Multiplexer(s).
Unit <pdp8_rf> synthesized.
Synthesizing Unit <pdp8_io>.
Related source file is "../../rtl/pdp8_io.v".
Found 1-bit 4-to-1 multiplexer for signal <io_clear_ac>.
Found 12-bit 4-to-1 multiplexer for signal <io_data_out>.
Found 1-bit 4-to-1 multiplexer for signal <io_data_avail>.
Summary:
inferred 13 Multiplexer(s).
inferred 14 Multiplexer(s).
Unit <pdp8_io> synthesized.
@@ -796,44 +802,43 @@ HDL Synthesis Report
Macro Statistics
# RAMs : 1
256x12-bit single-port distributed RAM : 1
# ROMs : 6
# ROMs : 10
16x25-bit ROM : 1
4x1-bit ROM : 4
4x1-bit ROM : 7
4x2-bit ROM : 1
8x8-bit ROM : 1
# Adders/Subtractors : 11
12-bit adder : 4
# Adders/Subtractors : 10
12-bit adder : 5
12-bit adder carry out : 2
13-bit adder : 2
15-bit adder : 1
20-bit adder : 1
4-bit adder : 1
# Counters : 11
11-bit up counter : 1
# Counters : 12
12-bit up counter : 1
13-bit up counter : 2
15-bit up counter : 1
2-bit up counter : 1
20-bit up counter : 1
25-bit up counter : 1
4-bit up counter : 2
8-bit up counter : 2
# Registers : 76
1-bit register : 51
8-bit up counter : 3
# Registers : 90
1-bit register : 67
10-bit register : 1
12-bit register : 8
15-bit register : 2
15-bit register : 1
16-bit register : 1
20-bit register : 1
3-bit register : 5
4-bit register : 2
7-bit register : 1
8-bit register : 4
# Comparators : 4
# Comparators : 5
12-bit comparator equal : 1
25-bit comparator equal : 1
4-bit comparator greatequal : 1
4-bit comparator lessequal : 1
# Multiplexers : 9
1-bit 4-to-1 multiplexer : 5
8-bit comparator less : 1
# Multiplexers : 11
1-bit 4-to-1 multiplexer : 7
12-bit 4-to-1 multiplexer : 2
3-bit 4-to-1 multiplexer : 1
4-bit 4-to-1 multiplexer : 1
@@ -859,15 +864,15 @@ Optimizing FSM <io/tf/db_state> on signal <db_state[1:15]> with one-hot encoding
0011 | 000000000001000
0100 | 000000000010000
0101 | 000000001000000
0110 | 000001000000000
0110 | 000010000000000
0111 | 000000000100000
1000 | 000100000000000
1001 | 000010000000000
1001 | 000001000000000
1010 | 001000000000000
1011 | 010000000000000
1100 | 100000000000000
1101 | 000000100000000
1111 | 000000010000000
1110 | 000000010000000
--------------------------
Analyzing FSM <FSM_5> for best encoding.
Optimizing FSM <io/tf/disk/ide_state> on signal <ide_state[1:23]> with one-hot encoding.
@@ -969,35 +974,35 @@ Macro Statistics
# FSMs : 7
# RAMs : 1
256x12-bit single-port distributed RAM : 1
# ROMs : 6
# ROMs : 10
16x25-bit ROM : 1
4x1-bit ROM : 4
4x1-bit ROM : 7
4x2-bit ROM : 1
8x8-bit ROM : 1
# Adders/Subtractors : 11
12-bit adder : 4
# Adders/Subtractors : 10
12-bit adder : 5
12-bit adder carry out : 2
13-bit adder : 2
15-bit adder : 1
20-bit adder : 1
4-bit adder : 1
# Counters : 11
11-bit up counter : 1
# Counters : 12
12-bit up counter : 1
13-bit up counter : 2
15-bit up counter : 1
2-bit up counter : 1
20-bit up counter : 1
25-bit up counter : 1
4-bit up counter : 2
8-bit up counter : 2
# Registers : 334
Flip-Flops : 334
# Comparators : 4
8-bit up counter : 3
# Registers : 315
Flip-Flops : 315
# Comparators : 5
12-bit comparator equal : 1
25-bit comparator equal : 1
4-bit comparator greatequal : 1
4-bit comparator lessequal : 1
# Multiplexers : 9
1-bit 4-to-1 multiplexer : 5
8-bit comparator less : 1
# Multiplexers : 11
1-bit 4-to-1 multiplexer : 7
12-bit 4-to-1 multiplexer : 2
3-bit 4-to-1 multiplexer : 1
4-bit 4-to-1 multiplexer : 1
@@ -1028,26 +1033,28 @@ Optimizing unit <pdp8_kw> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 12.
FlipFlop cpu/ac_0 has been replicated 2 time(s)
FlipFlop cpu/ac_1 has been replicated 1 time(s)
FlipFlop cpu/ac_2 has been replicated 1 time(s)
FlipFlop cpu/ac_6 has been replicated 1 time(s)
FlipFlop cpu/ir_0 has been replicated 5 time(s)
FlipFlop cpu/ac_0 has been replicated 1 time(s)
FlipFlop cpu/ir_0 has been replicated 4 time(s)
FlipFlop cpu/ir_1 has been replicated 5 time(s)
FlipFlop cpu/ir_2 has been replicated 5 time(s)
FlipFlop cpu/mb_0 has been replicated 4 time(s)
FlipFlop cpu/mb_1 has been replicated 3 time(s)
FlipFlop cpu/mb_2 has been replicated 2 time(s)
FlipFlop cpu/mb_3 has been replicated 5 time(s)
FlipFlop cpu/mb_4 has been replicated 4 time(s)
FlipFlop cpu/mb_5 has been replicated 4 time(s)
FlipFlop cpu/mb_6 has been replicated 3 time(s)
FlipFlop cpu/mb_7 has been replicated 3 time(s)
FlipFlop cpu/mb_1 has been replicated 4 time(s)
FlipFlop cpu/mb_2 has been replicated 5 time(s)
FlipFlop cpu/mb_3 has been replicated 6 time(s)
FlipFlop cpu/mb_4 has been replicated 5 time(s)
FlipFlop cpu/mb_5 has been replicated 5 time(s)
FlipFlop cpu/mb_6 has been replicated 5 time(s)
FlipFlop cpu/mb_7 has been replicated 4 time(s)
FlipFlop cpu/mb_8 has been replicated 4 time(s)
FlipFlop cpu/state_0 has been replicated 5 time(s)
FlipFlop cpu/state_1 has been replicated 5 time(s)
FlipFlop cpu/state_2 has been replicated 3 time(s)
FlipFlop cpu/state_3 has been replicated 4 time(s)
FlipFlop cpu/state_2 has been replicated 5 time(s)
FlipFlop cpu/state_3 has been replicated 5 time(s)
FlipFlop io/tf/db_state_FFd7 has been replicated 9 time(s)
FlipFlop io/tf/db_state_FFd8 has been replicated 9 time(s)
FlipFlop io/tf/db_state_FFd9 has been replicated 1 time(s)
FlipFlop io/tf/disk/ide_state_FFd6 has been replicated 1 time(s)
FlipFlop io/tf/disk/ide_state_FFd8 has been replicated 1 time(s)
Final Macro Processing ...
@@ -1059,8 +1066,8 @@ Unit <top> processed.
Final Register Report
Macro Statistics
# Registers : 506
Flip-Flops : 506
# Registers : 533
Flip-Flops : 533
=========================================================================
@@ -1089,37 +1096,38 @@ Design Statistics
# IOs : 116
Cell Usage :
# BELS : 2133
# BELS : 2231
# GND : 1
# INV : 23
# LUT1 : 180
# LUT2 : 132
# LUT2_D : 5
# LUT2_L : 4
# LUT3 : 226
# LUT3_D : 22
# LUT3_L : 8
# LUT4 : 809
# LUT4_D : 45
# LUT4_L : 109
# MUXCY : 221
# MUXF5 : 133
# INV : 22
# LUT1 : 155
# LUT2 : 140
# LUT2_D : 10
# LUT2_L : 10
# LUT3 : 249
# LUT3_D : 32
# LUT3_L : 27
# LUT4 : 879
# LUT4_D : 46
# LUT4_L : 126
# MULT_AND : 19
# MUXCY : 215
# MUXF5 : 91
# MUXF6 : 12
# VCC : 1
# XORCY : 202
# FlipFlops/Latches : 506
# XORCY : 196
# FlipFlops/Latches : 533
# FD : 26
# FDC : 30
# FDCE : 51
# FDE : 11
# FDE : 8
# FDP : 2
# FDPE : 3
# FDR : 164
# FDRE : 90
# FDRS : 109
# FDR : 117
# FDRE : 112
# FDRS : 163
# FDRSE : 4
# FDS : 3
# FDSE : 13
# FDSE : 14
# RAMS : 96
# RAM32X1S : 96
# Clock Buffers : 3
@@ -1137,10 +1145,10 @@ Device utilization summary:
Selected Device : 3s1000ft256-5
Number of Slices: 922 out of 7680 12%
Number of Slice Flip Flops: 506 out of 15360 3%
Number of 4 input LUTs: 1755 out of 15360 11%
Number used as logic: 1563
Number of Slices: 990 out of 7680 12%
Number of Slice Flip Flops: 533 out of 15360 3%
Number of 4 input LUTs: 1888 out of 15360 12%
Number used as logic: 1696
Number used as RAMs: 192
Number of IOs: 116
Number of bonded IOBs: 89 out of 173 51%
@@ -1156,33 +1164,33 @@ NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
Clock Information:
------------------
--------------------------------------+-----------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
--------------------------------------+-----------------------------+-------+
sysclk | BUFGP | 42 |
reset_sw/slowclk | NONE(reset_sw/hold_9) | 11 |
clk1 | BUFG | 491 |
io/tt/baud_rate_generator/rx_baud_clk1| BUFG | 30 |
io/tt/baud_rate_generator/tx_baud_clk | NONE(io/tt/tt_uart/tx_cnt_0)| 16 |
io/kw/kw_src_clk | NONE(io/kw/kw_ctr_7) | 12 |
--------------------------------------+-----------------------------+-------+
--------------------------------------+---------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
--------------------------------------+---------------------------+-------+
sysclk | BUFGP | 42 |
reset_sw/slowclk | NONE(reset_sw/hold_2) | 11 |
clk1 | BUFG | 518 |
io/tt/baud_rate_generator/rx_baud_clk1| BUFG | 30 |
io/tt/baud_rate_generator/tx_baud_clk | NONE(io/tt/tt_uart/tx_out)| 16 |
io/kw/kw_src_clk | NONE(io/kw/kw_ctr_4) | 12 |
--------------------------------------+---------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+---------------------------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+---------------------------------------------+-------+
reset(reset_sw/out28:O) | NONE(io/tt/baud_rate_generator/tx_clk_div_9)| 86 |
-----------------------------------+---------------------------------------------+-------+
-----------------------------------+--------------------------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+--------------------------------------------+-------+
reset(reset_sw/out28:O) | NONE(io/tt/baud_rate_generator/tx_baud_clk)| 86 |
-----------------------------------+--------------------------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 12.757ns (Maximum Frequency: 78.388MHz)
Minimum period: 11.549ns (Maximum Frequency: 86.585MHz)
Minimum input arrival time before clock: 7.558ns
Maximum output required time after clock: 18.769ns
Maximum output required time after clock: 15.972ns
Maximum combinational path delay: No path found
Timing Detail:
@@ -1191,10 +1199,10 @@ All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'sysclk'
Clock period: 6.815ns (frequency: 146.743MHz)
Clock period: 6.854ns (frequency: 145.909MHz)
Total number of paths / destination ports: 1112 / 69
-------------------------------------------------------------------------
Delay: 6.815ns (Levels of Logic = 2)
Delay: 6.854ns (Levels of Logic = 2)
Source: clk (FF)
Destination: clk (FF)
Source Clock: sysclk rising
@@ -1205,12 +1213,12 @@ Delay: 6.815ns (Levels of Logic = 2)
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDE:C->Q 1 0.626 0.681 clk (clk1)
BUFG:I->O 492 0.357 3.815 clk_BUFG (clk)
BUFG:I->O 519 0.357 3.854 clk_BUFG (clk)
INV:I->O 1 0.479 0.681 _not00011_INV_0 (_not0001)
FDE:D 0.176 clk
----------------------------------------
Total 6.815ns (1.638ns logic, 5.177ns route)
(24.0% logic, 76.0% route)
Total 6.854ns (1.638ns logic, 5.216ns route)
(23.9% logic, 76.1% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'reset_sw/slowclk'
@@ -1235,32 +1243,30 @@ Delay: 1.547ns (Levels of Logic = 0)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk1'
Clock period: 12.757ns (frequency: 78.388MHz)
Total number of paths / destination ports: 51556 / 1278
Clock period: 11.549ns (frequency: 86.585MHz)
Total number of paths / destination ports: 51473 / 1382
-------------------------------------------------------------------------
Delay: 12.757ns (Levels of Logic = 8)
Source: cpu/ir_0_1 (FF)
Destination: cpu/pc_11 (FF)
Delay: 11.549ns (Levels of Logic = 6)
Source: cpu/ir_2_1 (FF)
Destination: cpu/ac_3 (FF)
Source Clock: clk1 rising
Destination Clock: clk1 rising
Data Path: cpu/ir_0_1 to cpu/pc_11
Data Path: cpu/ir_2_1 to cpu/ac_3
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRE:C->Q 1 0.626 0.976 cpu/ir_0_1 (cpu/ir_0_1)
LUT4_D:I0->O 3 0.479 0.794 io/tt/_not00041_SW1 (N5714)
LUT4:I3->O 18 0.479 1.227 io/tt/io_data_out<1>1 (io/tt/N0)
LUT4_L:I3->LO 1 0.479 0.159 io/tt/io_selected1_1 (io/tt/io_selected1)
LUT4:I2->O 1 0.479 0.681 cpu/_xor002153 (cpu/_xor0021_map2064)
MUXF5:S->O 13 0.540 1.054 cpu/_xor0021140_SW0 (N5695)
LUT4:I2->O 15 0.479 1.010 cpu/_xor0021193 (cpu/_xor0021_map2091)
MUXF5:S->O 1 0.540 0.704 cpu/pc_mux<11>72_SW0 (N5783)
LUT4:I3->O 1 0.479 0.681 cpu/pc_mux<11>103 (cpu/pc_mux<11>_map1780)
FDRS:S 0.892 cpu/pc_11
FDRE:C->Q 5 0.626 1.078 cpu/ir_2_1 (cpu/ir_2_1)
LUT4:I0->O 1 0.479 0.740 io/tt/_not00041_SW0 (N6803)
LUT4:I2->O 17 0.479 1.166 io/tt/io_data_out<1>1 (io/tt/N0)
LUT4:I3->O 24 0.479 1.586 io/tt/io_selected1 (io/tt_io_selected)
LUT3:I2->O 3 0.479 0.830 io_data_avail1 (io_data_avail)
LUT4_D:I2->O 7 0.479 1.076 cpu/_mux0009<0>101 (cpu/N164)
LUT4:I1->O 1 0.479 0.681 cpu/_mux0009<7>170 (cpu/_mux0009<7>_map1750)
FDRS:S 0.892 cpu/ac_4
----------------------------------------
Total 12.757ns (5.472ns logic, 7.285ns route)
(42.9% logic, 57.1% route)
Total 11.549ns (4.392ns logic, 7.157ns route)
(38.0% logic, 62.0% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'io/tt/baud_rate_generator/rx_baud_clk1'
@@ -1279,7 +1285,7 @@ Delay: 6.319ns (Levels of Logic = 3)
---------------------------------------- ------------
FDCE:C->Q 12 0.626 1.245 io/tt/tt_uart/rx_cnt_2 (io/tt/tt_uart/rx_cnt_2)
LUT4:I0->O 3 0.479 1.066 io/tt/tt_uart/_cmp_eq00031 (io/tt/tt_uart/_cmp_eq0003)
LUT4:I0->O 1 0.479 0.740 io/tt/tt_uart/_not0028_SW0 (N769)
LUT4:I0->O 1 0.479 0.740 io/tt/tt_uart/_not0028_SW0 (N797)
LUT4:I2->O 1 0.479 0.681 io/tt/tt_uart/_not0028 (io/tt/tt_uart/_not0028)
FDCE:CE 0.524 io/tt/tt_uart/rx_busy
----------------------------------------
@@ -1288,27 +1294,28 @@ Delay: 6.319ns (Levels of Logic = 3)
=========================================================================
Timing constraint: Default period analysis for Clock 'io/tt/baud_rate_generator/tx_baud_clk'
Clock period: 5.009ns (frequency: 199.631MHz)
Total number of paths / destination ports: 77 / 22
Clock period: 4.443ns (frequency: 225.081MHz)
Total number of paths / destination ports: 84 / 22
-------------------------------------------------------------------------
Delay: 5.009ns (Levels of Logic = 3)
Source: io/tt/tt_uart/tx_cnt_1 (FF)
Delay: 4.443ns (Levels of Logic = 4)
Source: io/tt/tt_uart/tx_cnt_0 (FF)
Destination: io/tt/tt_uart/tx_out (FF)
Source Clock: io/tt/baud_rate_generator/tx_baud_clk rising
Destination Clock: io/tt/baud_rate_generator/tx_baud_clk rising
Data Path: io/tt/tt_uart/tx_cnt_1 to io/tt/tt_uart/tx_out
Data Path: io/tt/tt_uart/tx_cnt_0 to io/tt/tt_uart/tx_out
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 8 0.626 1.216 io/tt/tt_uart/tx_cnt_1 (io/tt/tt_uart/tx_cnt_1)
LUT4:I0->O 1 0.479 0.851 io/tt/tt_uart/_mux000649_SW0 (N6201)
LUT4:I1->O 1 0.479 0.704 io/tt/tt_uart/_mux000649 (io/tt/tt_uart/_mux0006_map385)
LUT4:I3->O 1 0.479 0.000 io/tt/tt_uart/_mux0006161 (io/tt/tt_uart/_mux0006)
FDCE:C->Q 9 0.626 1.250 io/tt/tt_uart/tx_cnt_0 (io/tt/tt_uart/tx_cnt_0)
LUT4:I0->O 1 0.479 0.000 io/tt/tt_uart/_mux0006129_G (N7342)
MUXF5:I1->O 2 0.314 0.804 io/tt/tt_uart/_mux0006129 (io/tt/tt_uart/_mux0006_map419)
LUT4:I2->O 1 0.479 0.000 io/tt/tt_uart/_mux0006161_F (N7343)
MUXF5:I0->O 1 0.314 0.000 io/tt/tt_uart/_mux0006161 (io/tt/tt_uart/_mux0006)
FDPE:D 0.176 io/tt/tt_uart/tx_out
----------------------------------------
Total 5.009ns (2.239ns logic, 2.770ns route)
(44.7% logic, 55.3% route)
Total 4.443ns (2.388ns logic, 2.055ns route)
(53.7% logic, 46.3% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'io/kw/kw_src_clk'
@@ -1397,35 +1404,36 @@ Offset: 1.572ns (Levels of Logic = 1)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk1'
Total number of paths / destination ports: 244 / 112
Total number of paths / destination ports: 254 / 121
-------------------------------------------------------------------------
Offset: 5.442ns (Levels of Logic = 14)
Source: sram1_io<1> (PAD)
Offset: 5.740ns (Levels of Logic = 15)
Source: sram1_io<0> (PAD)
Destination: io/tf/dma_wc_11 (FF)
Destination Clock: clk1 rising
Data Path: sram1_io<1> to io/tf/dma_wc_11
Data Path: sram1_io<0> to io/tf/dma_wc_11
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IOBUF:IO->O 3 0.715 1.066 sram1_io_1_IOBUF (N5468)
LUT3:I0->O 1 0.479 0.000 cpu/ext_ram_out<1>11 (N5565)
MUXCY:S->O 1 0.435 0.000 io/tf/Madd__add0001_cy<1> (io/tf/Madd__add0001_cy<1>)
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0001_cy<2> (io/tf/Madd__add0001_cy<2>)
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0001_cy<3> (io/tf/Madd__add0001_cy<3>)
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0001_cy<4> (io/tf/Madd__add0001_cy<4>)
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0001_cy<5> (io/tf/Madd__add0001_cy<5>)
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0001_cy<6> (io/tf/Madd__add0001_cy<6>)
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0001_cy<7> (io/tf/Madd__add0001_cy<7>)
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0001_cy<8> (io/tf/Madd__add0001_cy<8>)
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0001_cy<9> (io/tf/Madd__add0001_cy<9>)
MUXCY:CI->O 0 0.056 0.000 io/tf/Madd__add0001_cy<10> (io/tf/Madd__add0001_cy<10>)
XORCY:CI->O 2 0.786 0.745 io/tf/Madd__add0001_xor<11> (io/tf/_add0001<11>)
MUXF5:S->O 1 0.540 0.000 io/tf/_mux0009<11> (io/tf/_mux0009<11>)
FDR:D 0.176 io/tf/dma_addr_11
IOBUF:IO->O 4 0.715 1.074 sram1_io_0_IOBUF (N6517)
LUT2:I0->O 2 0.479 0.000 io/tf/Madd__add0002_lut<0> (io/tf/N222)
MUXCY:S->O 1 0.435 0.000 io/tf/Madd__add0002_cy<0> (io/tf/Madd__add0002_cy<0>)
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<1> (io/tf/Madd__add0002_cy<1>)
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<2> (io/tf/Madd__add0002_cy<2>)
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<3> (io/tf/Madd__add0002_cy<3>)
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<4> (io/tf/Madd__add0002_cy<4>)
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<5> (io/tf/Madd__add0002_cy<5>)
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<6> (io/tf/Madd__add0002_cy<6>)
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<7> (io/tf/Madd__add0002_cy<7>)
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<8> (io/tf/Madd__add0002_cy<8>)
MUXCY:CI->O 1 0.056 0.000 io/tf/Madd__add0002_cy<9> (io/tf/Madd__add0002_cy<9>)
MUXCY:CI->O 0 0.056 0.000 io/tf/Madd__add0002_cy<10> (io/tf/Madd__add0002_cy<10>)
XORCY:CI->O 2 0.786 1.040 io/tf/Madd__add0002_xor<11> (io/tf/_add0002<11>)
LUT4:I0->O 1 0.479 0.000 io/tf/_mux0009591 (N6574)
FDRS:D 0.176 io/tf/dma_addr_11
----------------------------------------
Total 5.442ns (3.631ns logic, 1.811ns route)
(66.7% logic, 33.3% route)
Total 5.740ns (3.625ns logic, 2.115ns route)
(63.2% logic, 36.8% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'io/tt/baud_rate_generator/rx_baud_clk1'
@@ -1448,30 +1456,30 @@ Offset: 1.572ns (Levels of Logic = 1)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk1'
Total number of paths / destination ports: 9225 / 56
Total number of paths / destination ports: 8901 / 56
-------------------------------------------------------------------------
Offset: 18.769ns (Levels of Logic = 9)
Source: io/tf/db_state_FFd7 (FF)
Offset: 15.972ns (Levels of Logic = 9)
Source: io/tf/disk/ide_state_FFd8 (FF)
Destination: sram1_io<0> (PAD)
Source Clock: clk1 rising
Data Path: io/tf/db_state_FFd7 to sram1_io<0>
Data Path: io/tf/disk/ide_state_FFd8 to sram1_io<0>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRS:C->Q 8 0.626 1.216 io/tf/db_state_FFd7 (io/tf/db_state_FFd7)
LUT2:I0->O 36 0.479 1.890 io/tf/ide_active1 (io/tf/ide_active)
LUT4:I0->O 384 0.479 3.289 io/tf/buff_addr<3>1 (io/tf/buff_addr<3>)
RAM32X1S:A3->O 1 0.793 0.851 io/tf/inst_Mram_mem96 (io/tf/N18)
LUT3:I1->O 1 0.479 0.000 io/tf/buff_addr<5>31 (io/tf/N512)
MUXF5:I0->O 1 0.314 0.000 io/tf/buff_addr<6>_f5_01 (io/tf/buff_addr<6>_f511)
MUXF6:I0->O 2 0.298 0.804 io/tf/inst_LPM_MUX_f6 (io/tf/buff_out<0>)
LUT4:I2->O 1 0.479 0.704 cpu/ram_data_out<0>32_SW1 (N6331)
FDR:C->Q 18 0.626 1.374 io/tf/disk/ide_state_FFd8 (io/tf/disk/ide_state_FFd8)
LUT2:I1->O 19 0.479 1.255 io/tf/disk/ide_state_Out201 (io/tf/disk/inc_offset)
LUT4:I3->O 12 0.479 0.950 io/tf/buff_addr<4>1_7 (io/tf/buff_addr<4>16)
RAM32X1S:A4->O 1 0.540 0.851 io/tf/inst_Mram_mem710 (io/tf/N34)
LUT3:I1->O 1 0.479 0.000 io/tf/buff_addr<5>1 (io/tf/N21)
MUXF5:I1->O 1 0.314 0.000 io/tf/buff_addr<6>_f5 (io/tf/buff_addr<6>_f5)
MUXF6:I1->O 4 0.298 1.074 io/tf/inst_LPM_MUX_f6 (io/tf/buff_out<0>)
LUT4:I0->O 1 0.479 0.704 cpu/ram_data_out<0>32_SW1 (N7303)
LUT4:I3->O 1 0.479 0.681 cpu/ram_data_out<0>32 (ram_data_in<0>)
IOBUF:I->IO 4.909 sram1_io_0_IOBUF (sram1_io<0>)
----------------------------------------
Total 18.769ns (9.335ns logic, 9.434ns route)
(49.7% logic, 50.3% route)
Total 15.972ns (9.082ns logic, 6.890ns route)
(56.9% logic, 43.1% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'io/tt/baud_rate_generator/tx_baud_clk'
@@ -1493,14 +1501,14 @@ Offset: 6.280ns (Levels of Logic = 1)
(88.1% logic, 11.9% route)
=========================================================================
CPU : 80.38 / 80.49 s | Elapsed : 81.00 / 82.00 s
CPU : 85.55 / 85.65 s | Elapsed : 87.00 / 87.00 s
-->
Total memory usage is 312076 kilobytes
Total memory usage is 318424 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 37 ( 0 filtered)
Number of warnings : 36 ( 0 filtered)
Number of infos : 15 ( 0 filtered)

10
xilinx/pdp8/top.twr
View File

@@ -31,8 +31,8 @@ Setup/Hold to clock sysclk
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
--------------+------------+------------+------------------+--------+
slideswitch<2>| 3.434(R)| -1.155(R)|sysclk_BUFGP | 0.000|
slideswitch<3>| 3.664(R)| -1.339(R)|sysclk_BUFGP | 0.000|
slideswitch<2>| 3.851(R)| -1.343(R)|sysclk_BUFGP | 0.000|
slideswitch<3>| 3.548(R)| -1.100(R)|sysclk_BUFGP | 0.000|
--------------+------------+------------+------------------+--------+
Clock to Setup on destination clock sysclk
@@ -40,18 +40,18 @@ Clock to Setup on destination clock sysclk
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
sysclk | 4.365| | | |
sysclk | 4.081| | | |
---------------+---------+---------+---------+---------+
Analysis completed Wed Apr 14 19:04:55 2010
Analysis completed Fri Apr 16 08:17:51 2010
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 266 MB
Peak Memory Usage: 267 MB

4
xilinx/pdp8/top.twx
View File

@@ -273,7 +273,7 @@
<twReport><twHead><twExecVer>Release 8.2i Trace </twExecVer><twCopyright>Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>trce -ise /home/brad/pdp8/xilinx/pdp8/pdp8.ise -intstyle ise -e 3 -l 3 -s 5
-xml top top.ncd -o top.twr top.pcf
</twCmdLine><twDesign>top.ncd</twDesign><twPCF>top.pcf</twPCF><twDevInfo arch="spartan3"><twDevName>xc3s1000</twDevName><twSpeedGrade>-5</twSpeedGrade><twSpeedVer>PRODUCTION 1.38 2006-05-03</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twErr"></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo>INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo>INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twBody><twErrRpt><twDataSheet twNameLen="15"><twSUH2ClkList twDestWidth = "14" twPhaseWidth = "12"><twDest>sysclk</twDest><twSUH2Clk ><twSrc>slideswitch&lt;2&gt;</twSrc><twSUHTime twInternalClk ="sysclk_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">3.434</twSU2ClkTime><twH2ClkTime twEdge="twRising">-1.155</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>slideswitch&lt;3&gt;</twSrc><twSUHTime twInternalClk ="sysclk_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">3.664</twSU2ClkTime><twH2ClkTime twEdge="twRising">-1.339</twH2ClkTime></twSUHTime></twSUH2Clk></twSUH2ClkList><twClk2SUList twDestWidth = "6"><twDest>sysclk</twDest><twClk2SU><twSrc>sysclk</twSrc><twRiseRise>4.365</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twErrRpt></twBody><twFoot><twTimestamp>Wed Apr 14 19:04:55 2010</twTimestamp></twFoot><twClientInfo><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
</twCmdLine><twDesign>top.ncd</twDesign><twPCF>top.pcf</twPCF><twDevInfo arch="spartan3"><twDevName>xc3s1000</twDevName><twSpeedGrade>-5</twSpeedGrade><twSpeedVer>PRODUCTION 1.38 2006-05-03</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twErr"></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo>INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo>INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twBody><twErrRpt><twDataSheet twNameLen="15"><twSUH2ClkList twDestWidth = "14" twPhaseWidth = "12"><twDest>sysclk</twDest><twSUH2Clk ><twSrc>slideswitch&lt;2&gt;</twSrc><twSUHTime twInternalClk ="sysclk_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">3.851</twSU2ClkTime><twH2ClkTime twEdge="twRising">-1.343</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>slideswitch&lt;3&gt;</twSrc><twSUHTime twInternalClk ="sysclk_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">3.548</twSU2ClkTime><twH2ClkTime twEdge="twRising">-1.100</twH2ClkTime></twSUHTime></twSUH2Clk></twSUH2ClkList><twClk2SUList twDestWidth = "6"><twDest>sysclk</twDest><twClk2SU><twSrc>sysclk</twSrc><twRiseRise>4.081</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twErrRpt></twBody><twFoot><twTimestamp>Fri Apr 16 08:17:51 2010</twTimestamp></twFoot><twClientInfo><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
Peak Memory Usage: 266 MB
Peak Memory Usage: 267 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>

2
xilinx/pdp8/top.unroutes
View File

@@ -1,7 +1,7 @@
Release 8.2i - par I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
Wed Apr 14 19:04:45 2010
Fri Apr 16 08:17:41 2010
There are 0 unrouted networks:

2
xilinx/pdp8/top_last_par.ncd
View File

File diff suppressed because one or more lines are too long

34
xilinx/pdp8/top_map.mrp
View File

@@ -9,32 +9,32 @@ Target Device : xc3s1000
Target Package : ft256
Target Speed : -5
Mapper Version : spartan3 -- $Revision: 1.34.32.1 $
Mapped Date : Wed Apr 14 19:03:24 2010
Mapped Date : Fri Apr 16 08:15:59 2010
Design Summary
--------------
Number of errors: 0
Number of warnings: 5
Number of warnings: 7
Logic Utilization:
Number of Slice Flip Flops: 492 out of 15,360 3%
Number of 4 input LUTs: 1,374 out of 15,360 8%
Number of Slice Flip Flops: 519 out of 15,360 3%
Number of 4 input LUTs: 1,532 out of 15,360 9%
Logic Distribution:
Number of occupied Slices: 1,045 out of 7,680 13%
Number of Slices containing only related logic: 1,045 out of 1,045 100%
Number of Slices containing unrelated logic: 0 out of 1,045 0%
Number of occupied Slices: 1,135 out of 7,680 14%
Number of Slices containing only related logic: 1,135 out of 1,135 100%
Number of Slices containing unrelated logic: 0 out of 1,135 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 1,749 out of 15,360 11%
Number used as logic: 1,374
Number used as a route-thru: 183
Total Number 4 input LUTs: 1,884 out of 15,360 12%
Number used as logic: 1,532
Number used as a route-thru: 160
Number used for 32x1 RAMs: 192
(Two LUTs used per 32x1 RAM)
Number of bonded IOBs: 89 out of 173 51%
IOB Flip Flops: 14
Number of GCLKs: 3 out of 8 37%
Total equivalent gate count for design: 38,965
Total equivalent gate count for design: 40,005
Additional JTAG gate count for IOBs: 4,272
Peak Memory Usage: 439 MB
Peak Memory Usage: 441 MB
NOTES:
@@ -93,8 +93,14 @@ WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
or/rx_baud_clk_BUFG" (output signal=io/tt/baud_rate_generator/rx_baud_clk)
has a mix of clock and non-clock loads. The non-clock loads are:
Pin D of io/tt/baud_rate_generator/rx_baud_clk
WARNING:Pack:266 - The function generator cpu/_mux0009<0>711 failed to merge
with F5 multiplexer cpu/_mux0009<4>199_SW1. There is a conflict for the
WARNING:Pack:266 - The function generator cpu/_mux0009<4>129 failed to merge
with F5 multiplexer cpu/_mux0009<7>73_SW11_f5. There is a conflict for the
FXMUX. The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator cpu/_mux0009<4>129 failed to merge
with F5 multiplexer cpu/_mux0009<8>73_SW11_f5. There is a conflict for the
FXMUX. The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator cpu/_mux0009<4>129 failed to merge
with F5 multiplexer cpu/_mux0009<6>73_SW1. There is a conflict for the
FXMUX. The design will exhibit suboptimal timing.
Section 3 - Informational

2
xilinx/pdp8/top_map.ncd
View File

File diff suppressed because one or more lines are too long

2
xilinx/pdp8/top_map.ngm
View File

File diff suppressed because one or more lines are too long

238
xilinx/pdp8/top_pad.csv
View File

@@ -1,7 +1,7 @@
#Release 8.2i - par I.31
#Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
#Wed Apr 14 19:04:43 2010
#Fri Apr 16 08:17:39 2010
#
## NOTE: This file is designed to be imported into a spreadsheet program
@@ -26,11 +26,11 @@ A4,,DIFFM,IO_L01P_0/VRN_0,UNUSED,,0,,,,,,,,,,
A5,,IOB,IO,UNUSED,,0,,,,,,,,,,
A6,,,VCCAUX,,,,,,,,2.5,,,,,
A7,,IOB,IO,UNUSED,,0,,,,,,,,,,
A8,sram1_io<13>,IOB,IO_L32P_0/GCLK6,TRISTATE,LVCMOS25,0,12,SLOW,NONE**,,,,,NO,NONE,
A9,sram1_io<8>,IOB,IO,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE,
A10,sram_oe_n,IOB,IO_L31N_1/VREF_1,OUTPUT,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE,
A8,,DIFFM,IO_L32P_0/GCLK6,UNUSED,,0,,,,,,,,,,
A9,,IOB,IO,UNUSED,,1,,,,,,,,,,
A10,,DIFFS,IO_L31N_1/VREF_1,UNUSED,,1,,,,,,,,,,
A11,,,VCCAUX,,,,,,,,2.5,,,,,
A12,sram1_io<4>,IOB,IO,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE,
A12,,IOB,IO,UNUSED,,1,,,,,,,,,,
A13,,DIFFS,IO_L10N_1/VREF_1,UNUSED,,1,,,,,,,,,,
A14,,DIFFS,IO_L01N_1/VRP_1,UNUSED,,1,,,,,,,,,,
A15,,,TDO,,,,,,,,,,,,,
@@ -38,72 +38,72 @@ A16,,,GND,,,,,,,,,,,,,
B1,,DIFFM,IO_L01P_7/VRN_7,UNUSED,,7,,,,,,,,,,
B2,,,GND,,,,,,,,,,,,,
B3,,,PROG_B,,,,,,,,,,,,,
B4,slideswitch<3>,IOB,IO_L01N_0/VRP_0,INPUT,LVCMOS25,0,,,,NONE,,,,NO,NONE,
B5,,DIFFM,IO_L25P_0,UNUSED,,0,,,,,,,,,,
B4,,DIFFS,IO_L01N_0/VRP_0,UNUSED,,0,,,,,,,,,,
B5,ide_da<0>,IOB,IO_L25P_0,OUTPUT,LVCMOS25,0,12,SLOW,NONE**,,,,,NO,NONE,
B6,,DIFFM,IO_L28P_0,UNUSED,,0,,,,,,,,,,
B7,,DIFFM,IO_L30P_0,UNUSED,,0,,,,,,,,,,
B8,sram1_io<14>,IOB,IO_L32N_0/GCLK7,TRISTATE,LVCMOS25,0,12,SLOW,NONE**,,,,,NO,NONE,
B8,,DIFFS,IO_L32N_0/GCLK7,UNUSED,,0,,,,,,,,,,
B9,,,GND,,,,,,,,,,,,,
B10,rs232_txd,IOB,IO_L31P_1,OUTPUT,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE,
B11,sram1_io<1>,IOB,IO_L29N_1,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE,
B12,sram1_io<10>,IOB,IO_L27N_1,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE,
B10,sram1_io<15>,IOB,IO_L31P_1,TRISTATE,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE,
B11,sram1_io<12>,IOB,IO_L29N_1,TRISTATE,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE,
B12,,DIFFS,IO_L27N_1,UNUSED,,1,,,,,,,,,,
B13,,DIFFM,IO_L10P_1,UNUSED,,1,,,,,,,,,,
B14,,DIFFM,IO_L01P_1/VRN_1,UNUSED,,1,,,,,,,,,,
B15,,,GND,,,,,,,,,,,,,
B16,,DIFFS,IO_L01N_2/VRP_2,UNUSED,,2,,,,,,,,,,
C1,slideswitch<0>,IOB,IO_L01N_7/VRP_7,INPUT,LVCMOS25,7,,,,NONE,,,,NO,NONE,
C2,,DIFFS,IO_L16N_7,UNUSED,,7,,,,,,,,,,
C3,,DIFFM,IO_L16P_7/VREF_7,UNUSED,,7,,,,,,,,,,
C1,,DIFFS,IO_L01N_7/VRP_7,UNUSED,,7,,,,,,,,,,
C2,sram2_io<9>,IOB,IO_L16N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
C3,sram2_lb_n,IOB,IO_L16P_7/VREF_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
C4,,,HSWAP_EN,,,,,,,,,,,,,
C5,,DIFFS,IO_L25N_0,UNUSED,,0,,,,,,,,,,
C5,slideswitch<3>,IOB,IO_L25N_0,INPUT,LVCMOS25,0,,,,NONE,,,,NO,NONE,
C6,,DIFFS,IO_L28N_0,UNUSED,,0,,,,,,,,,,
C7,,DIFFS,IO_L30N_0,UNUSED,,0,,,,,,,,,,
C8,,DIFFM,IO_L31P_0/VREF_0,UNUSED,,0,,,,,,,,,,
C9,sysclk,IOB,IO_L32N_1/GCLK5,INPUT,LVCMOS25,1,,,,NONE,,,,NO,NONE,
C10,sram1_io<6>,IOB,IO,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE,
C11,sram1_io<2>,IOB,IO_L29P_1,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE,
C12,sram1_io<5>,IOB,IO_L27P_1,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE,
C10,,IOB,IO,UNUSED,,1,,,,,,,,,,
C11,sram1_io<13>,IOB,IO_L29P_1,TRISTATE,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE,
C12,,DIFFM,IO_L27P_1,UNUSED,,1,,,,,,,,,,
C13,,,TMS,,,,,,,,,,,,,
C14,,,TCK,,,,,,,,,,,,,
C15,,DIFFS,IO_L16N_2,UNUSED,,2,,,,,,,,,,
C16,,DIFFM,IO_L01P_2/VRN_2,UNUSED,,2,,,,,,,,,,
D1,,DIFFS,IO_L17N_7,UNUSED,,7,,,,,,,,,,
D2,,DIFFM,IO_L17P_7,UNUSED,,7,,,,,,,,,,
D3,,DIFFM,IO_L19P_7,UNUSED,,7,,,,,,,,,,
D1,sram2_ub_n,IOB,IO_L17N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
D2,sram2_io<8>,IOB,IO_L17P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
D3,sram1_ub_n,IOB,IO_L19P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
D4,,,VCCINT,,,,,,,,1.2,,,,,
D5,slideswitch<2>,IOB,IO/VREF_0,INPUT,LVCMOS25,0,,,,NONE,,,,NO,NONE,
D6,,DIFFM,IO_L27P_0,UNUSED,,0,,,,,,,,,,
D5,slideswitch<0>,IOB,IO/VREF_0,INPUT,LVCMOS25,0,,,,NONE,,,,NO,NONE,
D6,slideswitch<2>,IOB,IO_L27P_0,INPUT,LVCMOS25,0,,,,NONE,,,,NO,NONE,
D7,,DIFFM,IO_L29P_0,UNUSED,,0,,,,,,,,,,
D8,sram1_io<15>,IOB,IO_L31N_0,TRISTATE,LVCMOS25,0,12,SLOW,NONE**,,,,,NO,NONE,
D9,sram1_io<12>,IOB,IO_L32P_1/GCLK4,TRISTATE,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE,
D10,sram1_io<7>,IOB,IO_L30N_1,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE,
D11,sram1_io<11>,IOB,IO_L28N_1,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE,
D12,sram1_io<9>,IOB,IO/VREF_1,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE,
D8,,DIFFS,IO_L31N_0,UNUSED,,0,,,,,,,,,,
D9,sram_a<17>,IOB,IO_L32P_1/GCLK4,OUTPUT,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE,
D10,,DIFFS,IO_L30N_1,UNUSED,,1,,,,,,,,,,
D11,,DIFFS,IO_L28N_1,UNUSED,,1,,,,,,,,,,
D12,,IOB,IO/VREF_1,UNUSED,,1,,,,,,,,,,
D13,,,VCCINT,,,,,,,,1.2,,,,,
D14,,DIFFM,IO_L16P_2,UNUSED,,2,,,,,,,,,,
D15,,DIFFS,IO_L17N_2,UNUSED,,2,,,,,,,,,,
D16,,DIFFM,IO_L17P_2/VREF_2,UNUSED,,2,,,,,,,,,,
E1,,DIFFS,IO_L20N_7,UNUSED,,7,,,,,,,,,,
E2,,DIFFM,IO_L20P_7,UNUSED,,7,,,,,,,,,,
E3,,DIFFS,IO_L19N_7/VREF_7,UNUSED,,7,,,,,,,,,,
E4,sram2_io<15>,IOB,IO_L21P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
E1,sram2_io<12>,IOB,IO_L20N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
E2,sram2_io<10>,IOB,IO_L20P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
E3,sram2_io<11>,IOB,IO_L19N_7/VREF_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
E4,sram2_io<14>,IOB,IO_L21P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
E5,,,VCCINT,,,,,,,,1.2,,,,,
E6,,DIFFS,IO_L27N_0,UNUSED,,0,,,,,,,,,,
E7,,DIFFS,IO_L29N_0,UNUSED,,0,,,,,,,,,,
E8,,,VCCO_0,,,0,,,,,2.50,,,,,
E9,,,VCCO_1,,,1,,,,,2.50,,,,,
E10,sram1_io<3>,IOB,IO_L30P_1,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE,
E11,sram1_io<0>,IOB,IO_L28P_1,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE,
E10,sram1_io<14>,IOB,IO_L30P_1,TRISTATE,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE,
E11,,DIFFM,IO_L28P_1,UNUSED,,1,,,,,,,,,,
E12,,,VCCINT,,,,,,,,1.2,,,,,
E13,,DIFFS,IO_L19N_2,UNUSED,,2,,,,,,,,,,
E14,,DIFFM,IO_L19P_2,UNUSED,,2,,,,,,,,,,
E15,,DIFFS,IO_L20N_2,UNUSED,,2,,,,,,,,,,
E16,,DIFFM,IO_L20P_2,UNUSED,,2,,,,,,,,,,
F1,,,VCCAUX,,,,,,,,2.5,,,,,
F2,sram_a<16>,IOB,IO_L22N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
F2,sram2_io<15>,IOB,IO_L22N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
F3,sram_a<15>,IOB,IO_L22P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
F4,sram2_io<13>,IOB,IO_L21N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
F5,sram2_io<12>,IOB,IO_L23P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
F5,,DIFFM,IO_L23P_7,UNUSED,,7,,,,,,,,,,
F6,,,GND,,,,,,,,,,,,,
F7,,,VCCO_0,,,0,,,,,2.50,,,,,
F8,,,VCCO_0,,,0,,,,,2.50,,,,,
@@ -112,29 +112,29 @@ F10,,,VCCO_1,,,1,,,,,2.50,,,,,
F11,,,GND,,,,,,,,,,,,,
F12,,DIFFS,IO_L21N_2,UNUSED,,2,,,,,,,,,,
F13,,DIFFM,IO_L21P_2,UNUSED,,2,,,,,,,,,,
F14,sram_a<14>,IOB,IO_L22N_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
F15,sram_a<10>,IOB,IO_L22P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
F14,,DIFFS,IO_L22N_2,UNUSED,,2,,,,,,,,,,
F15,,DIFFM,IO_L22P_2,UNUSED,,2,,,,,,,,,,
F16,,,VCCAUX,,,,,,,,2.5,,,,,
G1,sram2_io<0>,IOB,IO_L40P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
G2,button<3>,IOB,IO,INPUT,LVCMOS25,7,,,,IFD,,,,YES,NONE,
G3,sram1_lb_n,IOB,IO_L24N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
G4,sram2_io<14>,IOB,IO_L24P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
G5,sram1_ce_n,IOB,IO_L23N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
G1,ide_data_bus<2>,IOB,IO_L40P_7,BIDIR,LVCMOS25,7,12,SLOW,NONE**,IFD,,,,YES,NONE,
G2,ide_data_bus<7>,IOB,IO,BIDIR,LVCMOS25,7,12,SLOW,NONE**,IFD,,,,YES,NONE,
G3,ide_diow,IOB,IO_L24N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
G4,ide_dior,IOB,IO_L24P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
G5,sram_a<16>,IOB,IO_L23N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
G6,,,VCCO_7,,,7,,,,,2.50,,,,,
G7,,,GND,,,,,,,,,,,,,
G8,,,GND,,,,,,,,,,,,,
G9,,,GND,,,,,,,,,,,,,
G10,,,GND,,,,,,,,,,,,,
G11,,,VCCO_2,,,2,,,,,2.50,,,,,
G12,sram_a<13>,IOB,IO_L23N_2/VREF_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
G13,sram_a<1>,IOB,IO_L23P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
G14,sram_a<2>,IOB,IO_L24N_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
G15,sram_a<0>,IOB,IO_L24P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
G16,sram_a<8>,IOB,IO,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
H1,,DIFFS,IO_L40N_7/VREF_7,UNUSED,,7,,,,,,,,,,
G12,,DIFFS,IO_L23N_2/VREF_2,UNUSED,,2,,,,,,,,,,
G13,,DIFFM,IO_L23P_2,UNUSED,,2,,,,,,,,,,
G14,,DIFFS,IO_L24N_2,UNUSED,,2,,,,,,,,,,
G15,rs232_txd,IOB,IO_L24P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
G16,,DIFFM,IO,UNUSED,,2,,,,,,,,,,
H1,ide_data_bus<4>,IOB,IO_L40N_7/VREF_7,BIDIR,LVCMOS25,7,12,SLOW,NONE**,IFD,,,,YES,NONE,
H2,,,GND,,,,,,,,,,,,,
H3,sram2_io<5>,IOB,IO_L39N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
H4,,DIFFM,IO_L39P_7,UNUSED,,7,,,,,,,,,,
H3,ide_data_bus<5>,IOB,IO_L39N_7,BIDIR,LVCMOS25,7,12,SLOW,NONE**,IFD,,,,YES,NONE,
H4,button<3>,IOB,IO_L39P_7,INPUT,LVCMOS25,7,,,,IFD,,,,YES,NONE,
H5,,,VCCO_7,,,7,,,,,2.50,,,,,
H6,,,VCCO_7,,,7,,,,,2.50,,,,,
H7,,,GND,,,,,,,,,,,,,
@@ -143,14 +143,14 @@ H9,,,GND,,,,,,,,,,,,,
H10,,,GND,,,,,,,,,,,,,
H11,,,VCCO_2,,,2,,,,,2.50,,,,,
H12,,,VCCO_2,,,2,,,,,2.50,,,,,
H13,sram_a<9>,IOB,IO_L39N_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
H14,sram_a<3>,IOB,IO_L39P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
H15,sram_a<4>,IOB,IO_L40N_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
H16,sram_a<6>,IOB,IO_L40P_2/VREF_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
J1,sram_a<17>,IOB,IO_L40P_6/VREF_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
J2,,DIFFS,IO_L40N_6,UNUSED,,6,,,,,,,,,,
J3,ide_data_bus<15>,IOB,IO_L39P_6,TRISTATE,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
J4,ide_data_bus<13>,IOB,IO_L39N_6,TRISTATE,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
H13,,DIFFS,IO_L39N_2,UNUSED,,2,,,,,,,,,,
H14,sram_oe_n,IOB,IO_L39P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
H15,sram_we_n,IOB,IO_L40N_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
H16,sram_a<7>,IOB,IO_L40P_2/VREF_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
J1,ide_data_bus<0>,IOB,IO_L40P_6/VREF_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
J2,ide_data_bus<3>,IOB,IO_L40N_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
J3,ide_data_bus<10>,IOB,IO_L39P_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
J4,ide_data_bus<1>,IOB,IO_L39N_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
J5,,,VCCO_6,,,6,,,,,2.50,,,,,
J6,,,VCCO_6,,,6,,,,,2.50,,,,,
J7,,,GND,,,,,,,,,,,,,
@@ -159,84 +159,84 @@ J9,,,GND,,,,,,,,,,,,,
J10,,,GND,,,,,,,,,,,,,
J11,,,VCCO_3,,,3,,,,,2.50,,,,,
J12,,,VCCO_3,,,3,,,,,2.50,,,,,
J13,sram_a<5>,IOB,IO_L39P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
J14,sram_a<7>,IOB,IO_L39N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
J13,sram1_io<3>,IOB,IO_L39P_3,BIDIR,LVCMOS25,3,12,SLOW,NONE**,NONE,,,,NO,NONE,
J14,sram1_io<4>,IOB,IO_L39N_3,BIDIR,LVCMOS25,3,12,SLOW,NONE**,NONE,,,,NO,NONE,
J15,,,GND,,,,,,,,,,,,,
J16,sram_a<12>,IOB,IO_L40N_3/VREF_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
K1,sram2_io<7>,IOB,IO,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
K2,,DIFFM,IO_L24P_6,UNUSED,,6,,,,,,,,,,
K3,,DIFFS,IO_L24N_6/VREF_6,UNUSED,,6,,,,,,,,,,
K4,,DIFFM,IO_L23P_6,UNUSED,,6,,,,,,,,,,
K5,,DIFFS,IO_L23N_6,UNUSED,,6,,,,,,,,,,
J16,sram_a<0>,IOB,IO_L40N_3/VREF_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
K1,ide_data_bus<11>,IOB,IO,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
K2,ide_data_bus<9>,IOB,IO_L24P_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
K3,ide_data_bus<8>,IOB,IO_L24N_6/VREF_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
K4,ide_cs<0>,IOB,IO_L23P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
K5,ide_data_bus<6>,IOB,IO_L23N_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
K6,,,VCCO_6,,,6,,,,,2.50,,,,,
K7,,,GND,,,,,,,,,,,,,
K8,,,GND,,,,,,,,,,,,,
K9,,,GND,,,,,,,,,,,,,
K10,,,GND,,,,,,,,,,,,,
K11,,,VCCO_3,,,3,,,,,2.50,,,,,
K12,,DIFFS,IO_L23N_3,UNUSED,,3,,,,,,,,,,
K13,,DIFFM,IO_L24P_3,UNUSED,,3,,,,,,,,,,
K14,,DIFFS,IO_L24N_3,UNUSED,,3,,,,,,,,,,
K15,sram_we_n,IOB,IO,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
K16,sram_a<11>,IOB,IO_L40P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
K12,sram_a<13>,IOB,IO_L23N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
K13,sram1_io<6>,IOB,IO_L24P_3,BIDIR,LVCMOS25,3,12,SLOW,NONE**,NONE,,,,NO,NONE,
K14,sram_a<14>,IOB,IO_L24N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
K15,sram1_io<5>,IOB,IO,BIDIR,LVCMOS25,3,12,SLOW,NONE**,NONE,,,,NO,NONE,
K16,sram_a<3>,IOB,IO_L40P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
L1,,,VCCAUX,,,,,,,,2.5,,,,,
L2,sram2_io<11>,IOB,IO_L22P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
L3,sram2_io<10>,IOB,IO_L22N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
L4,sram2_ub_n,IOB,IO_L21P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
L5,sram1_ub_n,IOB,IO_L21N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
L2,ide_data_bus<12>,IOB,IO_L22P_6,TRISTATE,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
L3,ide_data_bus<14>,IOB,IO_L22N_6,TRISTATE,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
L4,ide_data_bus<15>,IOB,IO_L21P_6,TRISTATE,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
L5,ide_data_bus<13>,IOB,IO_L21N_6,TRISTATE,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
L6,,,GND,,,,,,,,,,,,,
L7,,,VCCO_5,,,5,,,,,2.50,,,,,
L8,,,VCCO_5,,,5,,,,,2.50,,,,,
L9,,,VCCO_4,,,4,,,,,2.50,,,,,
L10,,,VCCO_4,,,4,,,,,2.50,,,,,
L11,,,GND,,,,,,,,,,,,,
L12,,DIFFM,IO_L23P_3/VREF_3,UNUSED,,3,,,,,,,,,,
L13,,DIFFS,IO_L21N_3,UNUSED,,3,,,,,,,,,,
L14,,DIFFM,IO_L22P_3,UNUSED,,3,,,,,,,,,,
L15,,DIFFS,IO_L22N_3,UNUSED,,3,,,,,,,,,,
L12,sram_a<10>,IOB,IO_L23P_3/VREF_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
L13,sram_a<11>,IOB,IO_L21N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
L14,sram_a<9>,IOB,IO_L22P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
L15,sram_a<8>,IOB,IO_L22N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
L16,,,VCCAUX,,,,,,,,2.5,,,,,
M1,sram2_io<9>,IOB,IO_L20P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
M2,sram2_io<8>,IOB,IO_L20N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
M3,sram2_io<6>,IOB,IO_L19P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
M4,sram2_lb_n,IOB,IO_L19N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
M1,sram2_io<6>,IOB,IO_L20P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
M2,sram2_io<5>,IOB,IO_L20N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
M3,sram2_io<4>,IOB,IO_L19P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
M4,sram2_io<3>,IOB,IO_L19N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
M5,,,VCCINT,,,,,,,,1.2,,,,,
M6,,DIFFM,IO_L28P_5/D7,UNUSED,,5,,,,,,,,,,
M7,ide_data_bus<4>,IOB,IO_L30P_5,BIDIR,LVCMOS25,5,12,SLOW,NONE**,IFD,,,,YES,NONE,
M7,,DIFFM,IO_L30P_5,UNUSED,,5,,,,,,,,,,
M8,,,VCCO_5,,,5,,,,,2.50,,,,,
M9,,,VCCO_4,,,4,,,,,2.50,,,,,
M10,,DIFFS,IO_L29N_4,UNUSED,,4,,,,,,,,,,
M11,,DIFFS,IO_L27N_4/DIN/D0,UNUSED,,4,,,,,,,,,,
M11,sram_a<2>,IOB,IO_L27N_4/DIN/D0,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,,,NO,NONE,
M12,,,VCCINT,,,,,,,,1.2,,,,,
M13,,DIFFM,IO_L21P_3,UNUSED,,3,,,,,,,,,,
M13,sram_a<5>,IOB,IO_L21P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
M14,,DIFFS,IO_L19N_3,UNUSED,,3,,,,,,,,,,
M15,,DIFFM,IO_L20P_3,UNUSED,,3,,,,,,,,,,
M16,,DIFFS,IO_L20N_3,UNUSED,,3,,,,,,,,,,
N1,sram2_io<4>,IOB,IO_L17P_6/VREF_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
N2,sram2_io<3>,IOB,IO_L17N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
N3,sram2_io<2>,IOB,IO_L16P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
M15,sram_a<12>,IOB,IO_L20P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
M16,sram_a<6>,IOB,IO_L20N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
N1,sram2_io<2>,IOB,IO_L17P_6/VREF_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
N2,sram2_io<1>,IOB,IO_L17N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
N3,sram2_io<0>,IOB,IO_L16P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
N4,,,VCCINT,,,,,,,,1.2,,,,,
N5,,IOB,IO,UNUSED,,5,,,,,,,,,,
N6,,DIFFS,IO_L28N_5/D6,UNUSED,,5,,,,,,,,,,
N7,ide_data_bus<6>,IOB,IO_L30N_5,BIDIR,LVCMOS25,5,12,SLOW,NONE**,IFD,,,,YES,NONE,
N8,ide_da<2>,IOB,IO_L32P_5/GCLK2,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE,
N9,ide_data_bus<5>,IOB,IO_L31N_4/INIT_B,BIDIR,LVCMOS25,4,12,SLOW,NONE**,IFD,,,,YES,NONE,
N10,ide_data_bus<10>,IOB,IO_L29P_4,BIDIR,LVCMOS25,4,12,SLOW,NONE**,IFD,,,,YES,NONE,
N11,,DIFFM,IO_L27P_4/D1,UNUSED,,4,,,,,,,,,,
N12,,IOB,IO/VREF_4,UNUSED,,4,,,,,,,,,,
N7,,DIFFS,IO_L30N_5,UNUSED,,5,,,,,,,,,,
N8,sram1_io<0>,IOB,IO_L32P_5/GCLK2,BIDIR,LVCMOS25,5,12,SLOW,NONE**,NONE,,,,NO,NONE,
N9,sram1_io<8>,IOB,IO_L31N_4/INIT_B,BIDIR,LVCMOS25,4,12,SLOW,NONE**,NONE,,,,NO,NONE,
N10,,DIFFM,IO_L29P_4,UNUSED,,4,,,,,,,,,,
N11,rs232_rxd,IOB,IO_L27P_4/D1,INPUT,LVCMOS25,4,,,,IFD,,,,YES,NONE,
N12,sram1_io<9>,IOB,IO/VREF_4,BIDIR,LVCMOS25,4,12,SLOW,NONE**,NONE,,,,NO,NONE,
N13,,,VCCINT,,,,,,,,1.2,,,,,
N14,,DIFFM,IO_L19P_3,UNUSED,,3,,,,,,,,,,
N15,,DIFFM,IO_L17P_3/VREF_3,UNUSED,,3,,,,,,,,,,
N16,,DIFFS,IO_L17N_3,UNUSED,,3,,,,,,,,,,
P1,sram2_ce_n,IOB,IO_L01P_6/VRN_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
P2,sram2_io<1>,IOB,IO_L16N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
P2,sram1_lb_n,IOB,IO_L16N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
P3,,,M0,,,,,,,,,,,,,
P4,,,M2,,,,,,,,,,,,,
P5,ide_dior,IOB,IO_L27P_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE,
P6,ide_data_bus<7>,IOB,IO_L29P_5/VREF_5,BIDIR,LVCMOS25,5,12,SLOW,NONE**,IFD,,,,YES,NONE,
P5,ide_cs<1>,IOB,IO_L27P_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE,
P6,,DIFFM,IO_L29P_5/VREF_5,UNUSED,,5,,,,,,,,,,
P7,,IOB,IO,UNUSED,,5,,,,,,,,,,
P8,ide_da<1>,IOB,IO_L32N_5/GCLK3,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE,
P9,ide_da<0>,IOB,IO_L31P_4/DOUT/BUSY,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,,,NO,NONE,
P10,ide_data_bus<2>,IOB,IO_L30N_4/D2,BIDIR,LVCMOS25,4,12,SLOW,NONE**,IFD,,,,YES,NONE,
P8,sram1_io<1>,IOB,IO_L32N_5/GCLK3,BIDIR,LVCMOS25,5,12,SLOW,NONE**,NONE,,,,NO,NONE,
P9,sram_a<4>,IOB,IO_L31P_4/DOUT/BUSY,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,,,NO,NONE,
P10,,DIFFS,IO_L30N_4/D2,UNUSED,,4,,,,,,,,,,
P11,,DIFFS,IO_L28N_4,UNUSED,,4,,,,,,,,,,
P12,,DIFFS,IO_L25N_4,UNUSED,,4,,,,,,,,,,
P13,,IOB,IO/VREF_4,UNUSED,,4,,,,,,,,,,
@@ -245,14 +245,14 @@ P15,,DIFFS,IO_L16N_3,UNUSED,,3,,,,,,,,,,
P16,,DIFFS,IO_L01N_3/VRP_3,UNUSED,,3,,,,,,,,,,
R1,,DIFFS,IO_L01N_6/VRP_6,UNUSED,,6,,,,,,,,,,
R2,,,GND,,,,,,,,,,,,,
R3,ide_data_bus<12>,IOB,IO_L01P_5/CS_B,TRISTATE,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE,
R4,,DIFFM,IO_L10P_5/VRN_5,UNUSED,,5,,,,,,,,,,
R5,ide_diow,IOB,IO_L27N_5/VREF_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE,
R6,ide_data_bus<3>,IOB,IO_L29N_5,BIDIR,LVCMOS25,5,12,SLOW,NONE**,IFD,,,,YES,NONE,
R7,ide_data_bus<11>,IOB,IO_L31P_5/D5,BIDIR,LVCMOS25,5,12,SLOW,NONE**,IFD,,,,YES,NONE,
R3,,DIFFM,IO_L01P_5/CS_B,UNUSED,,5,,,,,,,,,,
R4,sram2_io<7>,IOB,IO_L10P_5/VRN_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE,
R5,ide_da<1>,IOB,IO_L27N_5/VREF_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE,
R6,,DIFFS,IO_L29N_5,UNUSED,,5,,,,,,,,,,
R7,,DIFFM,IO_L31P_5/D5,UNUSED,,5,,,,,,,,,,
R8,,,GND,,,,,,,,,,,,,
R9,ide_data_bus<9>,IOB,IO_L32N_4/GCLK1,BIDIR,LVCMOS25,4,12,SLOW,NONE**,IFD,,,,YES,NONE,
R10,ide_data_bus<1>,IOB,IO_L30P_4/D3,BIDIR,LVCMOS25,4,12,SLOW,NONE**,IFD,,,,YES,NONE,
R9,sram1_io<11>,IOB,IO_L32N_4/GCLK1,BIDIR,LVCMOS25,4,12,SLOW,NONE**,NONE,,,,NO,NONE,
R10,,DIFFM,IO_L30P_4/D3,UNUSED,,4,,,,,,,,,,
R11,,DIFFM,IO_L28P_4,UNUSED,,4,,,,,,,,,,
R12,,DIFFM,IO_L25P_4,UNUSED,,4,,,,,,,,,,
R13,,DIFFS,IO_L01N_4/VRP_4,UNUSED,,4,,,,,,,,,,
@@ -261,18 +261,18 @@ R15,,,GND,,,,,,,,,,,,,
R16,,DIFFM,IO_L01P_3/VRN_3,UNUSED,,3,,,,,,,,,,
T1,,,GND,,,,,,,,,,,,,
T2,,,M1,,,,,,,,,,,,,
T3,ide_data_bus<14>,IOB,IO_L01N_5/RDWR_B,TRISTATE,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE,
T3,,DIFFS,IO_L01N_5/RDWR_B,UNUSED,,5,,,,,,,,,,
T4,,DIFFS,IO_L10N_5/VRP_5,UNUSED,,5,,,,,,,,,,
T5,,IOB,IO,UNUSED,,5,,,,,,,,,,
T5,ide_da<2>,IOB,IO,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE,
T6,,,VCCAUX,,,,,,,,2.5,,,,,
T7,ide_cs<1>,IOB,IO_L31N_5/D4,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE,
T8,ide_cs<0>,IOB,IO/VREF_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE,
T9,ide_data_bus<8>,IOB,IO_L32P_4/GCLK0,BIDIR,LVCMOS25,4,12,SLOW,NONE**,IFD,,,,YES,NONE,
T10,ide_data_bus<0>,IOB,IO/VREF_4,BIDIR,LVCMOS25,4,12,SLOW,NONE**,IFD,,,,YES,NONE,
T7,,DIFFS,IO_L31N_5/D4,UNUSED,,5,,,,,,,,,,
T8,sram1_io<2>,IOB,IO/VREF_5,BIDIR,LVCMOS25,5,12,SLOW,NONE**,NONE,,,,NO,NONE,
T9,sram1_io<7>,IOB,IO_L32P_4/GCLK0,BIDIR,LVCMOS25,4,12,SLOW,NONE**,NONE,,,,NO,NONE,
T10,sram1_ce_n,IOB,IO/VREF_4,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,,,NO,NONE,
T11,,,VCCAUX,,,,,,,,2.5,,,,,
T12,,IOB,IO,UNUSED,,4,,,,,,,,,,
T12,sram_a<1>,IOB,IO,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,,,NO,NONE,
T13,,DIFFM,IO_L01P_4/VRN_4,UNUSED,,4,,,,,,,,,,
T14,rs232_rxd,IOB,IO,INPUT,LVCMOS25,4,,,,IFD,,,,YES,NONE,
T14,sram1_io<10>,IOB,IO,BIDIR,LVCMOS25,4,12,SLOW,NONE**,NONE,,,,NO,NONE,
T15,,,CCLK,,,,,,,,,,,,,
T16,,,GND,,,,,,,,,,,,,
1 #Release 8.2i - par I.31
2 #Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
3 #Wed Apr 14 19:04:43 2010 #Fri Apr 16 08:17:39 2010
4 #
5 ## NOTE: This file is designed to be imported into a spreadsheet program
6 # such as Microsoft Excel for viewing, printing and sorting. The |
7 # character is used as the data field separator. This file is also designed
26 A7,,IOB,IO,UNUSED,,0,,,,,,,,,,
27 A8,sram1_io<13>,IOB,IO_L32P_0/GCLK6,TRISTATE,LVCMOS25,0,12,SLOW,NONE**,,,,,NO,NONE, A8,,DIFFM,IO_L32P_0/GCLK6,UNUSED,,0,,,,,,,,,,
28 A9,sram1_io<8>,IOB,IO,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE, A9,,IOB,IO,UNUSED,,1,,,,,,,,,,
29 A10,sram_oe_n,IOB,IO_L31N_1/VREF_1,OUTPUT,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE, A10,,DIFFS,IO_L31N_1/VREF_1,UNUSED,,1,,,,,,,,,,
30 A11,,,VCCAUX,,,,,,,,2.5,,,,,
31 A12,sram1_io<4>,IOB,IO,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE, A12,,IOB,IO,UNUSED,,1,,,,,,,,,,
32 A13,,DIFFS,IO_L10N_1/VREF_1,UNUSED,,1,,,,,,,,,,
33 A14,,DIFFS,IO_L01N_1/VRP_1,UNUSED,,1,,,,,,,,,,
34 A15,,,TDO,,,,,,,,,,,,,
35 A16,,,GND,,,,,,,,,,,,,
36 B1,,DIFFM,IO_L01P_7/VRN_7,UNUSED,,7,,,,,,,,,,
38 B3,,,PROG_B,,,,,,,,,,,,,
39 B4,slideswitch<3>,IOB,IO_L01N_0/VRP_0,INPUT,LVCMOS25,0,,,,NONE,,,,NO,NONE, B4,,DIFFS,IO_L01N_0/VRP_0,UNUSED,,0,,,,,,,,,,
40 B5,,DIFFM,IO_L25P_0,UNUSED,,0,,,,,,,,,, B5,ide_da<0>,IOB,IO_L25P_0,OUTPUT,LVCMOS25,0,12,SLOW,NONE**,,,,,NO,NONE,
41 B6,,DIFFM,IO_L28P_0,UNUSED,,0,,,,,,,,,,
42 B7,,DIFFM,IO_L30P_0,UNUSED,,0,,,,,,,,,,
43 B8,sram1_io<14>,IOB,IO_L32N_0/GCLK7,TRISTATE,LVCMOS25,0,12,SLOW,NONE**,,,,,NO,NONE, B8,,DIFFS,IO_L32N_0/GCLK7,UNUSED,,0,,,,,,,,,,
44 B9,,,GND,,,,,,,,,,,,,
45 B10,rs232_txd,IOB,IO_L31P_1,OUTPUT,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE, B10,sram1_io<15>,IOB,IO_L31P_1,TRISTATE,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE,
46 B11,sram1_io<1>,IOB,IO_L29N_1,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE, B11,sram1_io<12>,IOB,IO_L29N_1,TRISTATE,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE,
47 B12,sram1_io<10>,IOB,IO_L27N_1,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE, B12,,DIFFS,IO_L27N_1,UNUSED,,1,,,,,,,,,,
48 B13,,DIFFM,IO_L10P_1,UNUSED,,1,,,,,,,,,,
49 B14,,DIFFM,IO_L01P_1/VRN_1,UNUSED,,1,,,,,,,,,,
50 B15,,,GND,,,,,,,,,,,,,
51 B16,,DIFFS,IO_L01N_2/VRP_2,UNUSED,,2,,,,,,,,,,
52 C1,slideswitch<0>,IOB,IO_L01N_7/VRP_7,INPUT,LVCMOS25,7,,,,NONE,,,,NO,NONE, C1,,DIFFS,IO_L01N_7/VRP_7,UNUSED,,7,,,,,,,,,,
53 C2,,DIFFS,IO_L16N_7,UNUSED,,7,,,,,,,,,, C2,sram2_io<9>,IOB,IO_L16N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
54 C3,,DIFFM,IO_L16P_7/VREF_7,UNUSED,,7,,,,,,,,,, C3,sram2_lb_n,IOB,IO_L16P_7/VREF_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
55 C4,,,HSWAP_EN,,,,,,,,,,,,,
56 C5,,DIFFS,IO_L25N_0,UNUSED,,0,,,,,,,,,, C5,slideswitch<3>,IOB,IO_L25N_0,INPUT,LVCMOS25,0,,,,NONE,,,,NO,NONE,
57 C6,,DIFFS,IO_L28N_0,UNUSED,,0,,,,,,,,,,
58 C7,,DIFFS,IO_L30N_0,UNUSED,,0,,,,,,,,,,
59 C8,,DIFFM,IO_L31P_0/VREF_0,UNUSED,,0,,,,,,,,,,
60 C9,sysclk,IOB,IO_L32N_1/GCLK5,INPUT,LVCMOS25,1,,,,NONE,,,,NO,NONE,
61 C10,sram1_io<6>,IOB,IO,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE, C10,,IOB,IO,UNUSED,,1,,,,,,,,,,
62 C11,sram1_io<2>,IOB,IO_L29P_1,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE, C11,sram1_io<13>,IOB,IO_L29P_1,TRISTATE,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE,
63 C12,sram1_io<5>,IOB,IO_L27P_1,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE, C12,,DIFFM,IO_L27P_1,UNUSED,,1,,,,,,,,,,
64 C13,,,TMS,,,,,,,,,,,,,
65 C14,,,TCK,,,,,,,,,,,,,
66 C15,,DIFFS,IO_L16N_2,UNUSED,,2,,,,,,,,,,
67 C16,,DIFFM,IO_L01P_2/VRN_2,UNUSED,,2,,,,,,,,,,
68 D1,,DIFFS,IO_L17N_7,UNUSED,,7,,,,,,,,,, D1,sram2_ub_n,IOB,IO_L17N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
69 D2,,DIFFM,IO_L17P_7,UNUSED,,7,,,,,,,,,, D2,sram2_io<8>,IOB,IO_L17P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
70 D3,,DIFFM,IO_L19P_7,UNUSED,,7,,,,,,,,,, D3,sram1_ub_n,IOB,IO_L19P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
71 D4,,,VCCINT,,,,,,,,1.2,,,,,
72 D5,slideswitch<2>,IOB,IO/VREF_0,INPUT,LVCMOS25,0,,,,NONE,,,,NO,NONE, D5,slideswitch<0>,IOB,IO/VREF_0,INPUT,LVCMOS25,0,,,,NONE,,,,NO,NONE,
73 D6,,DIFFM,IO_L27P_0,UNUSED,,0,,,,,,,,,, D6,slideswitch<2>,IOB,IO_L27P_0,INPUT,LVCMOS25,0,,,,NONE,,,,NO,NONE,
74 D7,,DIFFM,IO_L29P_0,UNUSED,,0,,,,,,,,,,
75 D8,sram1_io<15>,IOB,IO_L31N_0,TRISTATE,LVCMOS25,0,12,SLOW,NONE**,,,,,NO,NONE, D8,,DIFFS,IO_L31N_0,UNUSED,,0,,,,,,,,,,
76 D9,sram1_io<12>,IOB,IO_L32P_1/GCLK4,TRISTATE,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE, D9,sram_a<17>,IOB,IO_L32P_1/GCLK4,OUTPUT,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE,
77 D10,sram1_io<7>,IOB,IO_L30N_1,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE, D10,,DIFFS,IO_L30N_1,UNUSED,,1,,,,,,,,,,
78 D11,sram1_io<11>,IOB,IO_L28N_1,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE, D11,,DIFFS,IO_L28N_1,UNUSED,,1,,,,,,,,,,
79 D12,sram1_io<9>,IOB,IO/VREF_1,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE, D12,,IOB,IO/VREF_1,UNUSED,,1,,,,,,,,,,
80 D13,,,VCCINT,,,,,,,,1.2,,,,,
81 D14,,DIFFM,IO_L16P_2,UNUSED,,2,,,,,,,,,,
82 D15,,DIFFS,IO_L17N_2,UNUSED,,2,,,,,,,,,,
83 D16,,DIFFM,IO_L17P_2/VREF_2,UNUSED,,2,,,,,,,,,,
84 E1,,DIFFS,IO_L20N_7,UNUSED,,7,,,,,,,,,, E1,sram2_io<12>,IOB,IO_L20N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
85 E2,,DIFFM,IO_L20P_7,UNUSED,,7,,,,,,,,,, E2,sram2_io<10>,IOB,IO_L20P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
86 E3,,DIFFS,IO_L19N_7/VREF_7,UNUSED,,7,,,,,,,,,, E3,sram2_io<11>,IOB,IO_L19N_7/VREF_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
87 E4,sram2_io<15>,IOB,IO_L21P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, E4,sram2_io<14>,IOB,IO_L21P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
88 E5,,,VCCINT,,,,,,,,1.2,,,,,
89 E6,,DIFFS,IO_L27N_0,UNUSED,,0,,,,,,,,,,
90 E7,,DIFFS,IO_L29N_0,UNUSED,,0,,,,,,,,,,
91 E8,,,VCCO_0,,,0,,,,,2.50,,,,,
92 E9,,,VCCO_1,,,1,,,,,2.50,,,,,
93 E10,sram1_io<3>,IOB,IO_L30P_1,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE, E10,sram1_io<14>,IOB,IO_L30P_1,TRISTATE,LVCMOS25,1,12,SLOW,NONE**,,,,,NO,NONE,
94 E11,sram1_io<0>,IOB,IO_L28P_1,BIDIR,LVCMOS25,1,12,SLOW,NONE**,NONE,,,,NO,NONE, E11,,DIFFM,IO_L28P_1,UNUSED,,1,,,,,,,,,,
95 E12,,,VCCINT,,,,,,,,1.2,,,,,
96 E13,,DIFFS,IO_L19N_2,UNUSED,,2,,,,,,,,,,
97 E14,,DIFFM,IO_L19P_2,UNUSED,,2,,,,,,,,,,
98 E15,,DIFFS,IO_L20N_2,UNUSED,,2,,,,,,,,,,
99 E16,,DIFFM,IO_L20P_2,UNUSED,,2,,,,,,,,,,
100 F1,,,VCCAUX,,,,,,,,2.5,,,,,
101 F2,sram_a<16>,IOB,IO_L22N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, F2,sram2_io<15>,IOB,IO_L22N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
102 F3,sram_a<15>,IOB,IO_L22P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
103 F4,sram2_io<13>,IOB,IO_L21N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
104 F5,sram2_io<12>,IOB,IO_L23P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, F5,,DIFFM,IO_L23P_7,UNUSED,,7,,,,,,,,,,
105 F6,,,GND,,,,,,,,,,,,,
106 F7,,,VCCO_0,,,0,,,,,2.50,,,,,
107 F8,,,VCCO_0,,,0,,,,,2.50,,,,,
108 F9,,,VCCO_1,,,1,,,,,2.50,,,,,
109 F10,,,VCCO_1,,,1,,,,,2.50,,,,,
112 F13,,DIFFM,IO_L21P_2,UNUSED,,2,,,,,,,,,,
113 F14,sram_a<14>,IOB,IO_L22N_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE, F14,,DIFFS,IO_L22N_2,UNUSED,,2,,,,,,,,,,
114 F15,sram_a<10>,IOB,IO_L22P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE, F15,,DIFFM,IO_L22P_2,UNUSED,,2,,,,,,,,,,
115 F16,,,VCCAUX,,,,,,,,2.5,,,,,
116 G1,sram2_io<0>,IOB,IO_L40P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, G1,ide_data_bus<2>,IOB,IO_L40P_7,BIDIR,LVCMOS25,7,12,SLOW,NONE**,IFD,,,,YES,NONE,
117 G2,button<3>,IOB,IO,INPUT,LVCMOS25,7,,,,IFD,,,,YES,NONE, G2,ide_data_bus<7>,IOB,IO,BIDIR,LVCMOS25,7,12,SLOW,NONE**,IFD,,,,YES,NONE,
118 G3,sram1_lb_n,IOB,IO_L24N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, G3,ide_diow,IOB,IO_L24N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
119 G4,sram2_io<14>,IOB,IO_L24P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, G4,ide_dior,IOB,IO_L24P_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
120 G5,sram1_ce_n,IOB,IO_L23N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, G5,sram_a<16>,IOB,IO_L23N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE,
121 G6,,,VCCO_7,,,7,,,,,2.50,,,,,
122 G7,,,GND,,,,,,,,,,,,,
123 G8,,,GND,,,,,,,,,,,,,
124 G9,,,GND,,,,,,,,,,,,,
125 G10,,,GND,,,,,,,,,,,,,
126 G11,,,VCCO_2,,,2,,,,,2.50,,,,,
127 G12,sram_a<13>,IOB,IO_L23N_2/VREF_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE, G12,,DIFFS,IO_L23N_2/VREF_2,UNUSED,,2,,,,,,,,,,
128 G13,sram_a<1>,IOB,IO_L23P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE, G13,,DIFFM,IO_L23P_2,UNUSED,,2,,,,,,,,,,
129 G14,sram_a<2>,IOB,IO_L24N_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE, G14,,DIFFS,IO_L24N_2,UNUSED,,2,,,,,,,,,,
130 G15,sram_a<0>,IOB,IO_L24P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE, G15,rs232_txd,IOB,IO_L24P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
131 G16,sram_a<8>,IOB,IO,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE, G16,,DIFFM,IO,UNUSED,,2,,,,,,,,,,
132 H1,,DIFFS,IO_L40N_7/VREF_7,UNUSED,,7,,,,,,,,,, H1,ide_data_bus<4>,IOB,IO_L40N_7/VREF_7,BIDIR,LVCMOS25,7,12,SLOW,NONE**,IFD,,,,YES,NONE,
133 H2,,,GND,,,,,,,,,,,,,
134 H3,sram2_io<5>,IOB,IO_L39N_7,OUTPUT,LVCMOS25,7,12,SLOW,NONE**,,,,,NO,NONE, H3,ide_data_bus<5>,IOB,IO_L39N_7,BIDIR,LVCMOS25,7,12,SLOW,NONE**,IFD,,,,YES,NONE,
135 H4,,DIFFM,IO_L39P_7,UNUSED,,7,,,,,,,,,, H4,button<3>,IOB,IO_L39P_7,INPUT,LVCMOS25,7,,,,IFD,,,,YES,NONE,
136 H5,,,VCCO_7,,,7,,,,,2.50,,,,,
137 H6,,,VCCO_7,,,7,,,,,2.50,,,,,
138 H7,,,GND,,,,,,,,,,,,,
139 H8,,,GND,,,,,,,,,,,,,
140 H9,,,GND,,,,,,,,,,,,,
143 H12,,,VCCO_2,,,2,,,,,2.50,,,,,
144 H13,sram_a<9>,IOB,IO_L39N_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE, H13,,DIFFS,IO_L39N_2,UNUSED,,2,,,,,,,,,,
145 H14,sram_a<3>,IOB,IO_L39P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE, H14,sram_oe_n,IOB,IO_L39P_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
146 H15,sram_a<4>,IOB,IO_L40N_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE, H15,sram_we_n,IOB,IO_L40N_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
147 H16,sram_a<6>,IOB,IO_L40P_2/VREF_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE, H16,sram_a<7>,IOB,IO_L40P_2/VREF_2,OUTPUT,LVCMOS25,2,12,SLOW,NONE**,,,,,NO,NONE,
148 J1,sram_a<17>,IOB,IO_L40P_6/VREF_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, J1,ide_data_bus<0>,IOB,IO_L40P_6/VREF_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
149 J2,,DIFFS,IO_L40N_6,UNUSED,,6,,,,,,,,,, J2,ide_data_bus<3>,IOB,IO_L40N_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
150 J3,ide_data_bus<15>,IOB,IO_L39P_6,TRISTATE,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, J3,ide_data_bus<10>,IOB,IO_L39P_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
151 J4,ide_data_bus<13>,IOB,IO_L39N_6,TRISTATE,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, J4,ide_data_bus<1>,IOB,IO_L39N_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
152 J5,,,VCCO_6,,,6,,,,,2.50,,,,,
153 J6,,,VCCO_6,,,6,,,,,2.50,,,,,
154 J7,,,GND,,,,,,,,,,,,,
155 J8,,,GND,,,,,,,,,,,,,
156 J9,,,GND,,,,,,,,,,,,,
159 J12,,,VCCO_3,,,3,,,,,2.50,,,,,
160 J13,sram_a<5>,IOB,IO_L39P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE, J13,sram1_io<3>,IOB,IO_L39P_3,BIDIR,LVCMOS25,3,12,SLOW,NONE**,NONE,,,,NO,NONE,
161 J14,sram_a<7>,IOB,IO_L39N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE, J14,sram1_io<4>,IOB,IO_L39N_3,BIDIR,LVCMOS25,3,12,SLOW,NONE**,NONE,,,,NO,NONE,
162 J15,,,GND,,,,,,,,,,,,,
163 J16,sram_a<12>,IOB,IO_L40N_3/VREF_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE, J16,sram_a<0>,IOB,IO_L40N_3/VREF_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
164 K1,sram2_io<7>,IOB,IO,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, K1,ide_data_bus<11>,IOB,IO,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
165 K2,,DIFFM,IO_L24P_6,UNUSED,,6,,,,,,,,,, K2,ide_data_bus<9>,IOB,IO_L24P_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
166 K3,,DIFFS,IO_L24N_6/VREF_6,UNUSED,,6,,,,,,,,,, K3,ide_data_bus<8>,IOB,IO_L24N_6/VREF_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
167 K4,,DIFFM,IO_L23P_6,UNUSED,,6,,,,,,,,,, K4,ide_cs<0>,IOB,IO_L23P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
168 K5,,DIFFS,IO_L23N_6,UNUSED,,6,,,,,,,,,, K5,ide_data_bus<6>,IOB,IO_L23N_6,BIDIR,LVCMOS25,6,12,SLOW,NONE**,IFD,,,,YES,NONE,
169 K6,,,VCCO_6,,,6,,,,,2.50,,,,,
170 K7,,,GND,,,,,,,,,,,,,
171 K8,,,GND,,,,,,,,,,,,,
172 K9,,,GND,,,,,,,,,,,,,
173 K10,,,GND,,,,,,,,,,,,,
174 K11,,,VCCO_3,,,3,,,,,2.50,,,,,
175 K12,,DIFFS,IO_L23N_3,UNUSED,,3,,,,,,,,,, K12,sram_a<13>,IOB,IO_L23N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
176 K13,,DIFFM,IO_L24P_3,UNUSED,,3,,,,,,,,,, K13,sram1_io<6>,IOB,IO_L24P_3,BIDIR,LVCMOS25,3,12,SLOW,NONE**,NONE,,,,NO,NONE,
177 K14,,DIFFS,IO_L24N_3,UNUSED,,3,,,,,,,,,, K14,sram_a<14>,IOB,IO_L24N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
178 K15,sram_we_n,IOB,IO,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE, K15,sram1_io<5>,IOB,IO,BIDIR,LVCMOS25,3,12,SLOW,NONE**,NONE,,,,NO,NONE,
179 K16,sram_a<11>,IOB,IO_L40P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE, K16,sram_a<3>,IOB,IO_L40P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
180 L1,,,VCCAUX,,,,,,,,2.5,,,,,
181 L2,sram2_io<11>,IOB,IO_L22P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, L2,ide_data_bus<12>,IOB,IO_L22P_6,TRISTATE,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
182 L3,sram2_io<10>,IOB,IO_L22N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, L3,ide_data_bus<14>,IOB,IO_L22N_6,TRISTATE,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
183 L4,sram2_ub_n,IOB,IO_L21P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, L4,ide_data_bus<15>,IOB,IO_L21P_6,TRISTATE,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
184 L5,sram1_ub_n,IOB,IO_L21N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, L5,ide_data_bus<13>,IOB,IO_L21N_6,TRISTATE,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
185 L6,,,GND,,,,,,,,,,,,,
186 L7,,,VCCO_5,,,5,,,,,2.50,,,,,
187 L8,,,VCCO_5,,,5,,,,,2.50,,,,,
188 L9,,,VCCO_4,,,4,,,,,2.50,,,,,
189 L10,,,VCCO_4,,,4,,,,,2.50,,,,,
190 L11,,,GND,,,,,,,,,,,,,
191 L12,,DIFFM,IO_L23P_3/VREF_3,UNUSED,,3,,,,,,,,,, L12,sram_a<10>,IOB,IO_L23P_3/VREF_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
192 L13,,DIFFS,IO_L21N_3,UNUSED,,3,,,,,,,,,, L13,sram_a<11>,IOB,IO_L21N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
193 L14,,DIFFM,IO_L22P_3,UNUSED,,3,,,,,,,,,, L14,sram_a<9>,IOB,IO_L22P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
194 L15,,DIFFS,IO_L22N_3,UNUSED,,3,,,,,,,,,, L15,sram_a<8>,IOB,IO_L22N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
195 L16,,,VCCAUX,,,,,,,,2.5,,,,,
196 M1,sram2_io<9>,IOB,IO_L20P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, M1,sram2_io<6>,IOB,IO_L20P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
197 M2,sram2_io<8>,IOB,IO_L20N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, M2,sram2_io<5>,IOB,IO_L20N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
198 M3,sram2_io<6>,IOB,IO_L19P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, M3,sram2_io<4>,IOB,IO_L19P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
199 M4,sram2_lb_n,IOB,IO_L19N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, M4,sram2_io<3>,IOB,IO_L19N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
200 M5,,,VCCINT,,,,,,,,1.2,,,,,
201 M6,,DIFFM,IO_L28P_5/D7,UNUSED,,5,,,,,,,,,,
202 M7,ide_data_bus<4>,IOB,IO_L30P_5,BIDIR,LVCMOS25,5,12,SLOW,NONE**,IFD,,,,YES,NONE, M7,,DIFFM,IO_L30P_5,UNUSED,,5,,,,,,,,,,
203 M8,,,VCCO_5,,,5,,,,,2.50,,,,,
204 M9,,,VCCO_4,,,4,,,,,2.50,,,,,
205 M10,,DIFFS,IO_L29N_4,UNUSED,,4,,,,,,,,,,
206 M11,,DIFFS,IO_L27N_4/DIN/D0,UNUSED,,4,,,,,,,,,, M11,sram_a<2>,IOB,IO_L27N_4/DIN/D0,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,,,NO,NONE,
207 M12,,,VCCINT,,,,,,,,1.2,,,,,
208 M13,,DIFFM,IO_L21P_3,UNUSED,,3,,,,,,,,,, M13,sram_a<5>,IOB,IO_L21P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
209 M14,,DIFFS,IO_L19N_3,UNUSED,,3,,,,,,,,,,
210 M15,,DIFFM,IO_L20P_3,UNUSED,,3,,,,,,,,,, M15,sram_a<12>,IOB,IO_L20P_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
211 M16,,DIFFS,IO_L20N_3,UNUSED,,3,,,,,,,,,, M16,sram_a<6>,IOB,IO_L20N_3,OUTPUT,LVCMOS25,3,12,SLOW,NONE**,,,,,NO,NONE,
212 N1,sram2_io<4>,IOB,IO_L17P_6/VREF_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, N1,sram2_io<2>,IOB,IO_L17P_6/VREF_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
213 N2,sram2_io<3>,IOB,IO_L17N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, N2,sram2_io<1>,IOB,IO_L17N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
214 N3,sram2_io<2>,IOB,IO_L16P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, N3,sram2_io<0>,IOB,IO_L16P_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
215 N4,,,VCCINT,,,,,,,,1.2,,,,,
216 N5,,IOB,IO,UNUSED,,5,,,,,,,,,,
217 N6,,DIFFS,IO_L28N_5/D6,UNUSED,,5,,,,,,,,,,
218 N7,ide_data_bus<6>,IOB,IO_L30N_5,BIDIR,LVCMOS25,5,12,SLOW,NONE**,IFD,,,,YES,NONE, N7,,DIFFS,IO_L30N_5,UNUSED,,5,,,,,,,,,,
219 N8,ide_da<2>,IOB,IO_L32P_5/GCLK2,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE, N8,sram1_io<0>,IOB,IO_L32P_5/GCLK2,BIDIR,LVCMOS25,5,12,SLOW,NONE**,NONE,,,,NO,NONE,
220 N9,ide_data_bus<5>,IOB,IO_L31N_4/INIT_B,BIDIR,LVCMOS25,4,12,SLOW,NONE**,IFD,,,,YES,NONE, N9,sram1_io<8>,IOB,IO_L31N_4/INIT_B,BIDIR,LVCMOS25,4,12,SLOW,NONE**,NONE,,,,NO,NONE,
221 N10,ide_data_bus<10>,IOB,IO_L29P_4,BIDIR,LVCMOS25,4,12,SLOW,NONE**,IFD,,,,YES,NONE, N10,,DIFFM,IO_L29P_4,UNUSED,,4,,,,,,,,,,
222 N11,,DIFFM,IO_L27P_4/D1,UNUSED,,4,,,,,,,,,, N11,rs232_rxd,IOB,IO_L27P_4/D1,INPUT,LVCMOS25,4,,,,IFD,,,,YES,NONE,
223 N12,,IOB,IO/VREF_4,UNUSED,,4,,,,,,,,,, N12,sram1_io<9>,IOB,IO/VREF_4,BIDIR,LVCMOS25,4,12,SLOW,NONE**,NONE,,,,NO,NONE,
224 N13,,,VCCINT,,,,,,,,1.2,,,,,
225 N14,,DIFFM,IO_L19P_3,UNUSED,,3,,,,,,,,,,
226 N15,,DIFFM,IO_L17P_3/VREF_3,UNUSED,,3,,,,,,,,,,
227 N16,,DIFFS,IO_L17N_3,UNUSED,,3,,,,,,,,,,
228 P1,sram2_ce_n,IOB,IO_L01P_6/VRN_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
229 P2,sram2_io<1>,IOB,IO_L16N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE, P2,sram1_lb_n,IOB,IO_L16N_6,OUTPUT,LVCMOS25,6,12,SLOW,NONE**,,,,,NO,NONE,
230 P3,,,M0,,,,,,,,,,,,,
231 P4,,,M2,,,,,,,,,,,,,
232 P5,ide_dior,IOB,IO_L27P_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE, P5,ide_cs<1>,IOB,IO_L27P_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE,
233 P6,ide_data_bus<7>,IOB,IO_L29P_5/VREF_5,BIDIR,LVCMOS25,5,12,SLOW,NONE**,IFD,,,,YES,NONE, P6,,DIFFM,IO_L29P_5/VREF_5,UNUSED,,5,,,,,,,,,,
234 P7,,IOB,IO,UNUSED,,5,,,,,,,,,,
235 P8,ide_da<1>,IOB,IO_L32N_5/GCLK3,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE, P8,sram1_io<1>,IOB,IO_L32N_5/GCLK3,BIDIR,LVCMOS25,5,12,SLOW,NONE**,NONE,,,,NO,NONE,
236 P9,ide_da<0>,IOB,IO_L31P_4/DOUT/BUSY,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,,,NO,NONE, P9,sram_a<4>,IOB,IO_L31P_4/DOUT/BUSY,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,,,NO,NONE,
237 P10,ide_data_bus<2>,IOB,IO_L30N_4/D2,BIDIR,LVCMOS25,4,12,SLOW,NONE**,IFD,,,,YES,NONE, P10,,DIFFS,IO_L30N_4/D2,UNUSED,,4,,,,,,,,,,
238 P11,,DIFFS,IO_L28N_4,UNUSED,,4,,,,,,,,,,
239 P12,,DIFFS,IO_L25N_4,UNUSED,,4,,,,,,,,,,
240 P13,,IOB,IO/VREF_4,UNUSED,,4,,,,,,,,,,
241 P14,,DIFFM,IO_L16P_3,UNUSED,,3,,,,,,,,,,
242 P15,,DIFFS,IO_L16N_3,UNUSED,,3,,,,,,,,,,
245 R2,,,GND,,,,,,,,,,,,,
246 R3,ide_data_bus<12>,IOB,IO_L01P_5/CS_B,TRISTATE,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE, R3,,DIFFM,IO_L01P_5/CS_B,UNUSED,,5,,,,,,,,,,
247 R4,,DIFFM,IO_L10P_5/VRN_5,UNUSED,,5,,,,,,,,,, R4,sram2_io<7>,IOB,IO_L10P_5/VRN_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE,
248 R5,ide_diow,IOB,IO_L27N_5/VREF_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE, R5,ide_da<1>,IOB,IO_L27N_5/VREF_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE,
249 R6,ide_data_bus<3>,IOB,IO_L29N_5,BIDIR,LVCMOS25,5,12,SLOW,NONE**,IFD,,,,YES,NONE, R6,,DIFFS,IO_L29N_5,UNUSED,,5,,,,,,,,,,
250 R7,ide_data_bus<11>,IOB,IO_L31P_5/D5,BIDIR,LVCMOS25,5,12,SLOW,NONE**,IFD,,,,YES,NONE, R7,,DIFFM,IO_L31P_5/D5,UNUSED,,5,,,,,,,,,,
251 R8,,,GND,,,,,,,,,,,,,
252 R9,ide_data_bus<9>,IOB,IO_L32N_4/GCLK1,BIDIR,LVCMOS25,4,12,SLOW,NONE**,IFD,,,,YES,NONE, R9,sram1_io<11>,IOB,IO_L32N_4/GCLK1,BIDIR,LVCMOS25,4,12,SLOW,NONE**,NONE,,,,NO,NONE,
253 R10,ide_data_bus<1>,IOB,IO_L30P_4/D3,BIDIR,LVCMOS25,4,12,SLOW,NONE**,IFD,,,,YES,NONE, R10,,DIFFM,IO_L30P_4/D3,UNUSED,,4,,,,,,,,,,
254 R11,,DIFFM,IO_L28P_4,UNUSED,,4,,,,,,,,,,
255 R12,,DIFFM,IO_L25P_4,UNUSED,,4,,,,,,,,,,
256 R13,,DIFFS,IO_L01N_4/VRP_4,UNUSED,,4,,,,,,,,,,
257 R14,,,DONE,,,,,,,,,,,,,
258 R15,,,GND,,,,,,,,,,,,,
261 T2,,,M1,,,,,,,,,,,,,
262 T3,ide_data_bus<14>,IOB,IO_L01N_5/RDWR_B,TRISTATE,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE, T3,,DIFFS,IO_L01N_5/RDWR_B,UNUSED,,5,,,,,,,,,,
263 T4,,DIFFS,IO_L10N_5/VRP_5,UNUSED,,5,,,,,,,,,,
264 T5,,IOB,IO,UNUSED,,5,,,,,,,,,, T5,ide_da<2>,IOB,IO,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE,
265 T6,,,VCCAUX,,,,,,,,2.5,,,,,
266 T7,ide_cs<1>,IOB,IO_L31N_5/D4,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE, T7,,DIFFS,IO_L31N_5/D4,UNUSED,,5,,,,,,,,,,
267 T8,ide_cs<0>,IOB,IO/VREF_5,OUTPUT,LVCMOS25,5,12,SLOW,NONE**,,,,,NO,NONE, T8,sram1_io<2>,IOB,IO/VREF_5,BIDIR,LVCMOS25,5,12,SLOW,NONE**,NONE,,,,NO,NONE,
268 T9,ide_data_bus<8>,IOB,IO_L32P_4/GCLK0,BIDIR,LVCMOS25,4,12,SLOW,NONE**,IFD,,,,YES,NONE, T9,sram1_io<7>,IOB,IO_L32P_4/GCLK0,BIDIR,LVCMOS25,4,12,SLOW,NONE**,NONE,,,,NO,NONE,
269 T10,ide_data_bus<0>,IOB,IO/VREF_4,BIDIR,LVCMOS25,4,12,SLOW,NONE**,IFD,,,,YES,NONE, T10,sram1_ce_n,IOB,IO/VREF_4,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,,,NO,NONE,
270 T11,,,VCCAUX,,,,,,,,2.5,,,,,
271 T12,,IOB,IO,UNUSED,,4,,,,,,,,,, T12,sram_a<1>,IOB,IO,OUTPUT,LVCMOS25,4,12,SLOW,NONE**,,,,,NO,NONE,
272 T13,,DIFFM,IO_L01P_4/VRN_4,UNUSED,,4,,,,,,,,,,
273 T14,rs232_rxd,IOB,IO,INPUT,LVCMOS25,4,,,,IFD,,,,YES,NONE, T14,sram1_io<10>,IOB,IO,BIDIR,LVCMOS25,4,12,SLOW,NONE**,NONE,,,,NO,NONE,
274 T15,,,CCLK,,,,,,,,,,,,,
275 T16,,,GND,,,,,,,,,,,,,
276 # -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
277 #
278 #* Default value.

238
xilinx/pdp8/top_pad.txt
View File

@@ -1,7 +1,7 @@
Release 8.2i - par I.31
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
Wed Apr 14 19:04:44 2010
Fri Apr 16 08:17:40 2010
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
@@ -27,11 +27,11 @@ Pinout by Pin Number:
|A5 | |IOB |IO |UNUSED | |0 | | | | | | | | | |
|A6 | | |VCCAUX | | | | | | | |2.5 | | | | |
|A7 | |IOB |IO |UNUSED | |0 | | | | | | | | | |
|A8 |sram1_io<13> |IOB |IO_L32P_0/GCLK6 |TRISTATE |LVCMOS25 |0 |12 |SLOW |NONE** | | | | |NO |NONE |
|A9 |sram1_io<8> |IOB |IO |BIDIR |LVCMOS25 |1 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|A10 |sram_oe_n |IOB |IO_L31N_1/VREF_1 |OUTPUT |LVCMOS25 |1 |12 |SLOW |NONE** | | | | |NO |NONE |
|A8 | |DIFFM |IO_L32P_0/GCLK6 |UNUSED | |0 | | | | | | | | | |
|A9 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|A10 | |DIFFS |IO_L31N_1/VREF_1 |UNUSED | |1 | | | | | | | | | |
|A11 | | |VCCAUX | | | | | | | |2.5 | | | | |
|A12 |sram1_io<4> |IOB |IO |BIDIR |LVCMOS25 |1 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|A12 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|A13 | |DIFFS |IO_L10N_1/VREF_1 |UNUSED | |1 | | | | | | | | | |
|A14 | |DIFFS |IO_L01N_1/VRP_1 |UNUSED | |1 | | | | | | | | | |
|A15 | | |TDO | | | | | | | | | | | | |
@@ -39,72 +39,72 @@ Pinout by Pin Number:
|B1 | |DIFFM |IO_L01P_7/VRN_7 |UNUSED | |7 | | | | | | | | | |
|B2 | | |GND | | | | | | | | | | | | |
|B3 | | |PROG_B | | | | | | | | | | | | |
|B4 |slideswitch<3> |IOB |IO_L01N_0/VRP_0 |INPUT |LVCMOS25 |0 | | | |NONE | | | |NO |NONE |
|B5 | |DIFFM |IO_L25P_0 |UNUSED | |0 | | | | | | | | | |
|B4 | |DIFFS |IO_L01N_0/VRP_0 |UNUSED | |0 | | | | | | | | | |
|B5 |ide_da<0> |IOB |IO_L25P_0 |OUTPUT |LVCMOS25 |0 |12 |SLOW |NONE** | | | | |NO |NONE |
|B6 | |DIFFM |IO_L28P_0 |UNUSED | |0 | | | | | | | | | |
|B7 | |DIFFM |IO_L30P_0 |UNUSED | |0 | | | | | | | | | |
|B8 |sram1_io<14> |IOB |IO_L32N_0/GCLK7 |TRISTATE |LVCMOS25 |0 |12 |SLOW |NONE** | | | | |NO |NONE |
|B8 | |DIFFS |IO_L32N_0/GCLK7 |UNUSED | |0 | | | | | | | | | |
|B9 | | |GND | | | | | | | | | | | | |
|B10 |rs232_txd |IOB |IO_L31P_1 |OUTPUT |LVCMOS25 |1 |12 |SLOW |NONE** | | | | |NO |NONE |
|B11 |sram1_io<1> |IOB |IO_L29N_1 |BIDIR |LVCMOS25 |1 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|B12 |sram1_io<10> |IOB |IO_L27N_1 |BIDIR |LVCMOS25 |1 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|B10 |sram1_io<15> |IOB |IO_L31P_1 |TRISTATE |LVCMOS25 |1 |12 |SLOW |NONE** | | | | |NO |NONE |
|B11 |sram1_io<12> |IOB |IO_L29N_1 |TRISTATE |LVCMOS25 |1 |12 |SLOW |NONE** | | | | |NO |NONE |
|B12 | |DIFFS |IO_L27N_1 |UNUSED | |1 | | | | | | | | | |
|B13 | |DIFFM |IO_L10P_1 |UNUSED | |1 | | | | | | | | | |
|B14 | |DIFFM |IO_L01P_1/VRN_1 |UNUSED | |1 | | | | | | | | | |
|B15 | | |GND | | | | | | | | | | | | |
|B16 | |DIFFS |IO_L01N_2/VRP_2 |UNUSED | |2 | | | | | | | | | |
|C1 |slideswitch<0> |IOB |IO_L01N_7/VRP_7 |INPUT |LVCMOS25 |7 | | | |NONE | | | |NO |NONE |
|C2 | |DIFFS |IO_L16N_7 |UNUSED | |7 | | | | | | | | | |
|C3 | |DIFFM |IO_L16P_7/VREF_7 |UNUSED | |7 | | | | | | | | | |
|C1 | |DIFFS |IO_L01N_7/VRP_7 |UNUSED | |7 | | | | | | | | | |
|C2 |sram2_io<9> |IOB |IO_L16N_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|C3 |sram2_lb_n |IOB |IO_L16P_7/VREF_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|C4 | | |HSWAP_EN | | | | | | | | | | | | |
|C5 | |DIFFS |IO_L25N_0 |UNUSED | |0 | | | | | | | | | |
|C5 |slideswitch<3> |IOB |IO_L25N_0 |INPUT |LVCMOS25 |0 | | | |NONE | | | |NO |NONE |
|C6 | |DIFFS |IO_L28N_0 |UNUSED | |0 | | | | | | | | | |
|C7 | |DIFFS |IO_L30N_0 |UNUSED | |0 | | | | | | | | | |
|C8 | |DIFFM |IO_L31P_0/VREF_0 |UNUSED | |0 | | | | | | | | | |
|C9 |sysclk |IOB |IO_L32N_1/GCLK5 |INPUT |LVCMOS25 |1 | | | |NONE | | | |NO |NONE |
|C10 |sram1_io<6> |IOB |IO |BIDIR |LVCMOS25 |1 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|C11 |sram1_io<2> |IOB |IO_L29P_1 |BIDIR |LVCMOS25 |1 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|C12 |sram1_io<5> |IOB |IO_L27P_1 |BIDIR |LVCMOS25 |1 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|C10 | |IOB |IO |UNUSED | |1 | | | | | | | | | |
|C11 |sram1_io<13> |IOB |IO_L29P_1 |TRISTATE |LVCMOS25 |1 |12 |SLOW |NONE** | | | | |NO |NONE |
|C12 | |DIFFM |IO_L27P_1 |UNUSED | |1 | | | | | | | | | |
|C13 | | |TMS | | | | | | | | | | | | |
|C14 | | |TCK | | | | | | | | | | | | |
|C15 | |DIFFS |IO_L16N_2 |UNUSED | |2 | | | | | | | | | |
|C16 | |DIFFM |IO_L01P_2/VRN_2 |UNUSED | |2 | | | | | | | | | |
|D1 | |DIFFS |IO_L17N_7 |UNUSED | |7 | | | | | | | | | |
|D2 | |DIFFM |IO_L17P_7 |UNUSED | |7 | | | | | | | | | |
|D3 | |DIFFM |IO_L19P_7 |UNUSED | |7 | | | | | | | | | |
|D1 |sram2_ub_n |IOB |IO_L17N_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|D2 |sram2_io<8> |IOB |IO_L17P_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|D3 |sram1_ub_n |IOB |IO_L19P_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|D4 | | |VCCINT | | | | | | | |1.2 | | | | |
|D5 |slideswitch<2> |IOB |IO/VREF_0 |INPUT |LVCMOS25 |0 | | | |NONE | | | |NO |NONE |
|D6 | |DIFFM |IO_L27P_0 |UNUSED | |0 | | | | | | | | | |
|D5 |slideswitch<0> |IOB |IO/VREF_0 |INPUT |LVCMOS25 |0 | | | |NONE | | | |NO |NONE |
|D6 |slideswitch<2> |IOB |IO_L27P_0 |INPUT |LVCMOS25 |0 | | | |NONE | | | |NO |NONE |
|D7 | |DIFFM |IO_L29P_0 |UNUSED | |0 | | | | | | | | | |
|D8 |sram1_io<15> |IOB |IO_L31N_0 |TRISTATE |LVCMOS25 |0 |12 |SLOW |NONE** | | | | |NO |NONE |
|D9 |sram1_io<12> |IOB |IO_L32P_1/GCLK4 |TRISTATE |LVCMOS25 |1 |12 |SLOW |NONE** | | | | |NO |NONE |
|D10 |sram1_io<7> |IOB |IO_L30N_1 |BIDIR |LVCMOS25 |1 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|D11 |sram1_io<11> |IOB |IO_L28N_1 |BIDIR |LVCMOS25 |1 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|D12 |sram1_io<9> |IOB |IO/VREF_1 |BIDIR |LVCMOS25 |1 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|D8 | |DIFFS |IO_L31N_0 |UNUSED | |0 | | | | | | | | | |
|D9 |sram_a<17> |IOB |IO_L32P_1/GCLK4 |OUTPUT |LVCMOS25 |1 |12 |SLOW |NONE** | | | | |NO |NONE |
|D10 | |DIFFS |IO_L30N_1 |UNUSED | |1 | | | | | | | | | |
|D11 | |DIFFS |IO_L28N_1 |UNUSED | |1 | | | | | | | | | |
|D12 | |IOB |IO/VREF_1 |UNUSED | |1 | | | | | | | | | |
|D13 | | |VCCINT | | | | | | | |1.2 | | | | |
|D14 | |DIFFM |IO_L16P_2 |UNUSED | |2 | | | | | | | | | |
|D15 | |DIFFS |IO_L17N_2 |UNUSED | |2 | | | | | | | | | |
|D16 | |DIFFM |IO_L17P_2/VREF_2 |UNUSED | |2 | | | | | | | | | |
|E1 | |DIFFS |IO_L20N_7 |UNUSED | |7 | | | | | | | | | |
|E2 | |DIFFM |IO_L20P_7 |UNUSED | |7 | | | | | | | | | |
|E3 | |DIFFS |IO_L19N_7/VREF_7 |UNUSED | |7 | | | | | | | | | |
|E4 |sram2_io<15> |IOB |IO_L21P_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|E1 |sram2_io<12> |IOB |IO_L20N_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|E2 |sram2_io<10> |IOB |IO_L20P_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|E3 |sram2_io<11> |IOB |IO_L19N_7/VREF_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|E4 |sram2_io<14> |IOB |IO_L21P_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|E5 | | |VCCINT | | | | | | | |1.2 | | | | |
|E6 | |DIFFS |IO_L27N_0 |UNUSED | |0 | | | | | | | | | |
|E7 | |DIFFS |IO_L29N_0 |UNUSED | |0 | | | | | | | | | |
|E8 | | |VCCO_0 | | |0 | | | | |2.50 | | | | |
|E9 | | |VCCO_1 | | |1 | | | | |2.50 | | | | |
|E10 |sram1_io<3> |IOB |IO_L30P_1 |BIDIR |LVCMOS25 |1 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|E11 |sram1_io<0> |IOB |IO_L28P_1 |BIDIR |LVCMOS25 |1 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|E10 |sram1_io<14> |IOB |IO_L30P_1 |TRISTATE |LVCMOS25 |1 |12 |SLOW |NONE** | | | | |NO |NONE |
|E11 | |DIFFM |IO_L28P_1 |UNUSED | |1 | | | | | | | | | |
|E12 | | |VCCINT | | | | | | | |1.2 | | | | |
|E13 | |DIFFS |IO_L19N_2 |UNUSED | |2 | | | | | | | | | |
|E14 | |DIFFM |IO_L19P_2 |UNUSED | |2 | | | | | | | | | |
|E15 | |DIFFS |IO_L20N_2 |UNUSED | |2 | | | | | | | | | |
|E16 | |DIFFM |IO_L20P_2 |UNUSED | |2 | | | | | | | | | |
|F1 | | |VCCAUX | | | | | | | |2.5 | | | | |
|F2 |sram_a<16> |IOB |IO_L22N_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|F2 |sram2_io<15> |IOB |IO_L22N_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|F3 |sram_a<15> |IOB |IO_L22P_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|F4 |sram2_io<13> |IOB |IO_L21N_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|F5 |sram2_io<12> |IOB |IO_L23P_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|F5 | |DIFFM |IO_L23P_7 |UNUSED | |7 | | | | | | | | | |
|F6 | | |GND | | | | | | | | | | | | |
|F7 | | |VCCO_0 | | |0 | | | | |2.50 | | | | |
|F8 | | |VCCO_0 | | |0 | | | | |2.50 | | | | |
@@ -113,29 +113,29 @@ Pinout by Pin Number:
|F11 | | |GND | | | | | | | | | | | | |
|F12 | |DIFFS |IO_L21N_2 |UNUSED | |2 | | | | | | | | | |
|F13 | |DIFFM |IO_L21P_2 |UNUSED | |2 | | | | | | | | | |
|F14 |sram_a<14> |IOB |IO_L22N_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | | | |NO |NONE |
|F15 |sram_a<10> |IOB |IO_L22P_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | | | |NO |NONE |
|F14 | |DIFFS |IO_L22N_2 |UNUSED | |2 | | | | | | | | | |
|F15 | |DIFFM |IO_L22P_2 |UNUSED | |2 | | | | | | | | | |
|F16 | | |VCCAUX | | | | | | | |2.5 | | | | |
|G1 |sram2_io<0> |IOB |IO_L40P_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|G2 |button<3> |IOB |IO |INPUT |LVCMOS25 |7 | | | |IFD | | | |YES |NONE |
|G3 |sram1_lb_n |IOB |IO_L24N_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|G4 |sram2_io<14> |IOB |IO_L24P_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|G5 |sram1_ce_n |IOB |IO_L23N_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|G1 |ide_data_bus<2> |IOB |IO_L40P_7 |BIDIR |LVCMOS25 |7 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|G2 |ide_data_bus<7> |IOB |IO |BIDIR |LVCMOS25 |7 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|G3 |ide_diow |IOB |IO_L24N_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|G4 |ide_dior |IOB |IO_L24P_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|G5 |sram_a<16> |IOB |IO_L23N_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|G6 | | |VCCO_7 | | |7 | | | | |2.50 | | | | |
|G7 | | |GND | | | | | | | | | | | | |
|G8 | | |GND | | | | | | | | | | | | |
|G9 | | |GND | | | | | | | | | | | | |
|G10 | | |GND | | | | | | | | | | | | |
|G11 | | |VCCO_2 | | |2 | | | | |2.50 | | | | |
|G12 |sram_a<13> |IOB |IO_L23N_2/VREF_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | | | |NO |NONE |
|G13 |sram_a<1> |IOB |IO_L23P_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | | | |NO |NONE |
|G14 |sram_a<2> |IOB |IO_L24N_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | | | |NO |NONE |
|G15 |sram_a<0> |IOB |IO_L24P_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | | | |NO |NONE |
|G16 |sram_a<8> |IOB |IO |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | | | |NO |NONE |
|H1 | |DIFFS |IO_L40N_7/VREF_7 |UNUSED | |7 | | | | | | | | | |
|G12 | |DIFFS |IO_L23N_2/VREF_2 |UNUSED | |2 | | | | | | | | | |
|G13 | |DIFFM |IO_L23P_2 |UNUSED | |2 | | | | | | | | | |
|G14 | |DIFFS |IO_L24N_2 |UNUSED | |2 | | | | | | | | | |
|G15 |rs232_txd |IOB |IO_L24P_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | | | |NO |NONE |
|G16 | |DIFFM |IO |UNUSED | |2 | | | | | | | | | |
|H1 |ide_data_bus<4> |IOB |IO_L40N_7/VREF_7 |BIDIR |LVCMOS25 |7 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|H2 | | |GND | | | | | | | | | | | | |
|H3 |sram2_io<5> |IOB |IO_L39N_7 |OUTPUT |LVCMOS25 |7 |12 |SLOW |NONE** | | | | |NO |NONE |
|H4 | |DIFFM |IO_L39P_7 |UNUSED | |7 | | | | | | | | | |
|H3 |ide_data_bus<5> |IOB |IO_L39N_7 |BIDIR |LVCMOS25 |7 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|H4 |button<3> |IOB |IO_L39P_7 |INPUT |LVCMOS25 |7 | | | |IFD | | | |YES |NONE |
|H5 | | |VCCO_7 | | |7 | | | | |2.50 | | | | |
|H6 | | |VCCO_7 | | |7 | | | | |2.50 | | | | |
|H7 | | |GND | | | | | | | | | | | | |
@@ -144,14 +144,14 @@ Pinout by Pin Number:
|H10 | | |GND | | | | | | | | | | | | |
|H11 | | |VCCO_2 | | |2 | | | | |2.50 | | | | |
|H12 | | |VCCO_2 | | |2 | | | | |2.50 | | | | |
|H13 |sram_a<9> |IOB |IO_L39N_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | | | |NO |NONE |
|H14 |sram_a<3> |IOB |IO_L39P_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | | | |NO |NONE |
|H15 |sram_a<4> |IOB |IO_L40N_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | | | |NO |NONE |
|H16 |sram_a<6> |IOB |IO_L40P_2/VREF_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | | | |NO |NONE |
|J1 |sram_a<17> |IOB |IO_L40P_6/VREF_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|J2 | |DIFFS |IO_L40N_6 |UNUSED | |6 | | | | | | | | | |
|J3 |ide_data_bus<15>|IOB |IO_L39P_6 |TRISTATE |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|J4 |ide_data_bus<13>|IOB |IO_L39N_6 |TRISTATE |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|H13 | |DIFFS |IO_L39N_2 |UNUSED | |2 | | | | | | | | | |
|H14 |sram_oe_n |IOB |IO_L39P_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | | | |NO |NONE |
|H15 |sram_we_n |IOB |IO_L40N_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | | | |NO |NONE |
|H16 |sram_a<7> |IOB |IO_L40P_2/VREF_2 |OUTPUT |LVCMOS25 |2 |12 |SLOW |NONE** | | | | |NO |NONE |
|J1 |ide_data_bus<0> |IOB |IO_L40P_6/VREF_6 |BIDIR |LVCMOS25 |6 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|J2 |ide_data_bus<3> |IOB |IO_L40N_6 |BIDIR |LVCMOS25 |6 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|J3 |ide_data_bus<10>|IOB |IO_L39P_6 |BIDIR |LVCMOS25 |6 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|J4 |ide_data_bus<1> |IOB |IO_L39N_6 |BIDIR |LVCMOS25 |6 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|J5 | | |VCCO_6 | | |6 | | | | |2.50 | | | | |
|J6 | | |VCCO_6 | | |6 | | | | |2.50 | | | | |
|J7 | | |GND | | | | | | | | | | | | |
@@ -160,84 +160,84 @@ Pinout by Pin Number:
|J10 | | |GND | | | | | | | | | | | | |
|J11 | | |VCCO_3 | | |3 | | | | |2.50 | | | | |
|J12 | | |VCCO_3 | | |3 | | | | |2.50 | | | | |
|J13 |sram_a<5> |IOB |IO_L39P_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|J14 |sram_a<7> |IOB |IO_L39N_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|J13 |sram1_io<3> |IOB |IO_L39P_3 |BIDIR |LVCMOS25 |3 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|J14 |sram1_io<4> |IOB |IO_L39N_3 |BIDIR |LVCMOS25 |3 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|J15 | | |GND | | | | | | | | | | | | |
|J16 |sram_a<12> |IOB |IO_L40N_3/VREF_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|K1 |sram2_io<7> |IOB |IO |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|K2 | |DIFFM |IO_L24P_6 |UNUSED | |6 | | | | | | | | | |
|K3 | |DIFFS |IO_L24N_6/VREF_6 |UNUSED | |6 | | | | | | | | | |
|K4 | |DIFFM |IO_L23P_6 |UNUSED | |6 | | | | | | | | | |
|K5 | |DIFFS |IO_L23N_6 |UNUSED | |6 | | | | | | | | | |
|J16 |sram_a<0> |IOB |IO_L40N_3/VREF_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|K1 |ide_data_bus<11>|IOB |IO |BIDIR |LVCMOS25 |6 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|K2 |ide_data_bus<9> |IOB |IO_L24P_6 |BIDIR |LVCMOS25 |6 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|K3 |ide_data_bus<8> |IOB |IO_L24N_6/VREF_6 |BIDIR |LVCMOS25 |6 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|K4 |ide_cs<0> |IOB |IO_L23P_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|K5 |ide_data_bus<6> |IOB |IO_L23N_6 |BIDIR |LVCMOS25 |6 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|K6 | | |VCCO_6 | | |6 | | | | |2.50 | | | | |
|K7 | | |GND | | | | | | | | | | | | |
|K8 | | |GND | | | | | | | | | | | | |
|K9 | | |GND | | | | | | | | | | | | |
|K10 | | |GND | | | | | | | | | | | | |
|K11 | | |VCCO_3 | | |3 | | | | |2.50 | | | | |
|K12 | |DIFFS |IO_L23N_3 |UNUSED | |3 | | | | | | | | | |
|K13 | |DIFFM |IO_L24P_3 |UNUSED | |3 | | | | | | | | | |
|K14 | |DIFFS |IO_L24N_3 |UNUSED | |3 | | | | | | | | | |
|K15 |sram_we_n |IOB |IO |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|K16 |sram_a<11> |IOB |IO_L40P_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|K12 |sram_a<13> |IOB |IO_L23N_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|K13 |sram1_io<6> |IOB |IO_L24P_3 |BIDIR |LVCMOS25 |3 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|K14 |sram_a<14> |IOB |IO_L24N_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|K15 |sram1_io<5> |IOB |IO |BIDIR |LVCMOS25 |3 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|K16 |sram_a<3> |IOB |IO_L40P_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|L1 | | |VCCAUX | | | | | | | |2.5 | | | | |
|L2 |sram2_io<11> |IOB |IO_L22P_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|L3 |sram2_io<10> |IOB |IO_L22N_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|L4 |sram2_ub_n |IOB |IO_L21P_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|L5 |sram1_ub_n |IOB |IO_L21N_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|L2 |ide_data_bus<12>|IOB |IO_L22P_6 |TRISTATE |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|L3 |ide_data_bus<14>|IOB |IO_L22N_6 |TRISTATE |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|L4 |ide_data_bus<15>|IOB |IO_L21P_6 |TRISTATE |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|L5 |ide_data_bus<13>|IOB |IO_L21N_6 |TRISTATE |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|L6 | | |GND | | | | | | | | | | | | |
|L7 | | |VCCO_5 | | |5 | | | | |2.50 | | | | |
|L8 | | |VCCO_5 | | |5 | | | | |2.50 | | | | |
|L9 | | |VCCO_4 | | |4 | | | | |2.50 | | | | |
|L10 | | |VCCO_4 | | |4 | | | | |2.50 | | | | |
|L11 | | |GND | | | | | | | | | | | | |
|L12 | |DIFFM |IO_L23P_3/VREF_3 |UNUSED | |3 | | | | | | | | | |
|L13 | |DIFFS |IO_L21N_3 |UNUSED | |3 | | | | | | | | | |
|L14 | |DIFFM |IO_L22P_3 |UNUSED | |3 | | | | | | | | | |
|L15 | |DIFFS |IO_L22N_3 |UNUSED | |3 | | | | | | | | | |
|L12 |sram_a<10> |IOB |IO_L23P_3/VREF_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|L13 |sram_a<11> |IOB |IO_L21N_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|L14 |sram_a<9> |IOB |IO_L22P_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|L15 |sram_a<8> |IOB |IO_L22N_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|L16 | | |VCCAUX | | | | | | | |2.5 | | | | |
|M1 |sram2_io<9> |IOB |IO_L20P_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|M2 |sram2_io<8> |IOB |IO_L20N_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|M3 |sram2_io<6> |IOB |IO_L19P_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|M4 |sram2_lb_n |IOB |IO_L19N_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|M1 |sram2_io<6> |IOB |IO_L20P_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|M2 |sram2_io<5> |IOB |IO_L20N_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|M3 |sram2_io<4> |IOB |IO_L19P_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|M4 |sram2_io<3> |IOB |IO_L19N_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|M5 | | |VCCINT | | | | | | | |1.2 | | | | |
|M6 | |DIFFM |IO_L28P_5/D7 |UNUSED | |5 | | | | | | | | | |
|M7 |ide_data_bus<4> |IOB |IO_L30P_5 |BIDIR |LVCMOS25 |5 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|M7 | |DIFFM |IO_L30P_5 |UNUSED | |5 | | | | | | | | | |
|M8 | | |VCCO_5 | | |5 | | | | |2.50 | | | | |
|M9 | | |VCCO_4 | | |4 | | | | |2.50 | | | | |
|M10 | |DIFFS |IO_L29N_4 |UNUSED | |4 | | | | | | | | | |
|M11 | |DIFFS |IO_L27N_4/DIN/D0 |UNUSED | |4 | | | | | | | | | |
|M11 |sram_a<2> |IOB |IO_L27N_4/DIN/D0 |OUTPUT |LVCMOS25 |4 |12 |SLOW |NONE** | | | | |NO |NONE |
|M12 | | |VCCINT | | | | | | | |1.2 | | | | |
|M13 | |DIFFM |IO_L21P_3 |UNUSED | |3 | | | | | | | | | |
|M13 |sram_a<5> |IOB |IO_L21P_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|M14 | |DIFFS |IO_L19N_3 |UNUSED | |3 | | | | | | | | | |
|M15 | |DIFFM |IO_L20P_3 |UNUSED | |3 | | | | | | | | | |
|M16 | |DIFFS |IO_L20N_3 |UNUSED | |3 | | | | | | | | | |
|N1 |sram2_io<4> |IOB |IO_L17P_6/VREF_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|N2 |sram2_io<3> |IOB |IO_L17N_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|N3 |sram2_io<2> |IOB |IO_L16P_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|M15 |sram_a<12> |IOB |IO_L20P_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|M16 |sram_a<6> |IOB |IO_L20N_3 |OUTPUT |LVCMOS25 |3 |12 |SLOW |NONE** | | | | |NO |NONE |
|N1 |sram2_io<2> |IOB |IO_L17P_6/VREF_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|N2 |sram2_io<1> |IOB |IO_L17N_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|N3 |sram2_io<0> |IOB |IO_L16P_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|N4 | | |VCCINT | | | | | | | |1.2 | | | | |
|N5 | |IOB |IO |UNUSED | |5 | | | | | | | | | |
|N6 | |DIFFS |IO_L28N_5/D6 |UNUSED | |5 | | | | | | | | | |
|N7 |ide_data_bus<6> |IOB |IO_L30N_5 |BIDIR |LVCMOS25 |5 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|N8 |ide_da<2> |IOB |IO_L32P_5/GCLK2 |OUTPUT |LVCMOS25 |5 |12 |SLOW |NONE** | | | | |NO |NONE |
|N9 |ide_data_bus<5> |IOB |IO_L31N_4/INIT_B |BIDIR |LVCMOS25 |4 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|N10 |ide_data_bus<10>|IOB |IO_L29P_4 |BIDIR |LVCMOS25 |4 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|N11 | |DIFFM |IO_L27P_4/D1 |UNUSED | |4 | | | | | | | | | |
|N12 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | | |
|N7 | |DIFFS |IO_L30N_5 |UNUSED | |5 | | | | | | | | | |
|N8 |sram1_io<0> |IOB |IO_L32P_5/GCLK2 |BIDIR |LVCMOS25 |5 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|N9 |sram1_io<8> |IOB |IO_L31N_4/INIT_B |BIDIR |LVCMOS25 |4 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|N10 | |DIFFM |IO_L29P_4 |UNUSED | |4 | | | | | | | | | |
|N11 |rs232_rxd |IOB |IO_L27P_4/D1 |INPUT |LVCMOS25 |4 | | | |IFD | | | |YES |NONE |
|N12 |sram1_io<9> |IOB |IO/VREF_4 |BIDIR |LVCMOS25 |4 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|N13 | | |VCCINT | | | | | | | |1.2 | | | | |
|N14 | |DIFFM |IO_L19P_3 |UNUSED | |3 | | | | | | | | | |
|N15 | |DIFFM |IO_L17P_3/VREF_3 |UNUSED | |3 | | | | | | | | | |
|N16 | |DIFFS |IO_L17N_3 |UNUSED | |3 | | | | | | | | | |
|P1 |sram2_ce_n |IOB |IO_L01P_6/VRN_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|P2 |sram2_io<1> |IOB |IO_L16N_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|P2 |sram1_lb_n |IOB |IO_L16N_6 |OUTPUT |LVCMOS25 |6 |12 |SLOW |NONE** | | | | |NO |NONE |
|P3 | | |M0 | | | | | | | | | | | | |
|P4 | | |M2 | | | | | | | | | | | | |
|P5 |ide_dior |IOB |IO_L27P_5 |OUTPUT |LVCMOS25 |5 |12 |SLOW |NONE** | | | | |NO |NONE |
|P6 |ide_data_bus<7> |IOB |IO_L29P_5/VREF_5 |BIDIR |LVCMOS25 |5 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|P5 |ide_cs<1> |IOB |IO_L27P_5 |OUTPUT |LVCMOS25 |5 |12 |SLOW |NONE** | | | | |NO |NONE |
|P6 | |DIFFM |IO_L29P_5/VREF_5 |UNUSED | |5 | | | | | | | | | |
|P7 | |IOB |IO |UNUSED | |5 | | | | | | | | | |
|P8 |ide_da<1> |IOB |IO_L32N_5/GCLK3 |OUTPUT |LVCMOS25 |5 |12 |SLOW |NONE** | | | | |NO |NONE |
|P9 |ide_da<0> |IOB |IO_L31P_4/DOUT/BUSY|OUTPUT |LVCMOS25 |4 |12 |SLOW |NONE** | | | | |NO |NONE |
|P10 |ide_data_bus<2> |IOB |IO_L30N_4/D2 |BIDIR |LVCMOS25 |4 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|P8 |sram1_io<1> |IOB |IO_L32N_5/GCLK3 |BIDIR |LVCMOS25 |5 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|P9 |sram_a<4> |IOB |IO_L31P_4/DOUT/BUSY|OUTPUT |LVCMOS25 |4 |12 |SLOW |NONE** | | | | |NO |NONE |
|P10 | |DIFFS |IO_L30N_4/D2 |UNUSED | |4 | | | | | | | | | |
|P11 | |DIFFS |IO_L28N_4 |UNUSED | |4 | | | | | | | | | |
|P12 | |DIFFS |IO_L25N_4 |UNUSED | |4 | | | | | | | | | |
|P13 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | | |
@@ -246,14 +246,14 @@ Pinout by Pin Number:
|P16 | |DIFFS |IO_L01N_3/VRP_3 |UNUSED | |3 | | | | | | | | | |
|R1 | |DIFFS |IO_L01N_6/VRP_6 |UNUSED | |6 | | | | | | | | | |
|R2 | | |GND | | | | | | | | | | | | |
|R3 |ide_data_bus<12>|IOB |IO_L01P_5/CS_B |TRISTATE |LVCMOS25 |5 |12 |SLOW |NONE** | | | | |NO |NONE |
|R4 | |DIFFM |IO_L10P_5/VRN_5 |UNUSED | |5 | | | | | | | | | |
|R5 |ide_diow |IOB |IO_L27N_5/VREF_5 |OUTPUT |LVCMOS25 |5 |12 |SLOW |NONE** | | | | |NO |NONE |
|R6 |ide_data_bus<3> |IOB |IO_L29N_5 |BIDIR |LVCMOS25 |5 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|R7 |ide_data_bus<11>|IOB |IO_L31P_5/D5 |BIDIR |LVCMOS25 |5 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|R3 | |DIFFM |IO_L01P_5/CS_B |UNUSED | |5 | | | | | | | | | |
|R4 |sram2_io<7> |IOB |IO_L10P_5/VRN_5 |OUTPUT |LVCMOS25 |5 |12 |SLOW |NONE** | | | | |NO |NONE |
|R5 |ide_da<1> |IOB |IO_L27N_5/VREF_5 |OUTPUT |LVCMOS25 |5 |12 |SLOW |NONE** | | | | |NO |NONE |
|R6 | |DIFFS |IO_L29N_5 |UNUSED | |5 | | | | | | | | | |
|R7 | |DIFFM |IO_L31P_5/D5 |UNUSED | |5 | | | | | | | | | |
|R8 | | |GND | | | | | | | | | | | | |
|R9 |ide_data_bus<9> |IOB |IO_L32N_4/GCLK1 |BIDIR |LVCMOS25 |4 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|R10 |ide_data_bus<1> |IOB |IO_L30P_4/D3 |BIDIR |LVCMOS25 |4 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|R9 |sram1_io<11> |IOB |IO_L32N_4/GCLK1 |BIDIR |LVCMOS25 |4 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|R10 | |DIFFM |IO_L30P_4/D3 |UNUSED | |4 | | | | | | | | | |
|R11 | |DIFFM |IO_L28P_4 |UNUSED | |4 | | | | | | | | | |
|R12 | |DIFFM |IO_L25P_4 |UNUSED | |4 | | | | | | | | | |
|R13 | |DIFFS |IO_L01N_4/VRP_4 |UNUSED | |4 | | | | | | | | | |
@@ -262,18 +262,18 @@ Pinout by Pin Number:
|R16 | |DIFFM |IO_L01P_3/VRN_3 |UNUSED | |3 | | | | | | | | | |
|T1 | | |GND | | | | | | | | | | | | |
|T2 | | |M1 | | | | | | | | | | | | |
|T3 |ide_data_bus<14>|IOB |IO_L01N_5/RDWR_B |TRISTATE |LVCMOS25 |5 |12 |SLOW |NONE** | | | | |NO |NONE |
|T3 | |DIFFS |IO_L01N_5/RDWR_B |UNUSED | |5 | | | | | | | | | |
|T4 | |DIFFS |IO_L10N_5/VRP_5 |UNUSED | |5 | | | | | | | | | |
|T5 | |IOB |IO |UNUSED | |5 | | | | | | | | | |
|T5 |ide_da<2> |IOB |IO |OUTPUT |LVCMOS25 |5 |12 |SLOW |NONE** | | | | |NO |NONE |
|T6 | | |VCCAUX | | | | | | | |2.5 | | | | |
|T7 |ide_cs<1> |IOB |IO_L31N_5/D4 |OUTPUT |LVCMOS25 |5 |12 |SLOW |NONE** | | | | |NO |NONE |
|T8 |ide_cs<0> |IOB |IO/VREF_5 |OUTPUT |LVCMOS25 |5 |12 |SLOW |NONE** | | | | |NO |NONE |
|T9 |ide_data_bus<8> |IOB |IO_L32P_4/GCLK0 |BIDIR |LVCMOS25 |4 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|T10 |ide_data_bus<0> |IOB |IO/VREF_4 |BIDIR |LVCMOS25 |4 |12 |SLOW |NONE** |IFD | | | |YES |NONE |
|T7 | |DIFFS |IO_L31N_5/D4 |UNUSED | |5 | | | | | | | | | |
|T8 |sram1_io<2> |IOB |IO/VREF_5 |BIDIR |LVCMOS25 |5 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|T9 |sram1_io<7> |IOB |IO_L32P_4/GCLK0 |BIDIR |LVCMOS25 |4 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|T10 |sram1_ce_n |IOB |IO/VREF_4 |OUTPUT |LVCMOS25 |4 |12 |SLOW |NONE** | | | | |NO |NONE |
|T11 | | |VCCAUX | | | | | | | |2.5 | | | | |
|T12 | |IOB |IO |UNUSED | |4 | | | | | | | | | |
|T12 |sram_a<1> |IOB |IO |OUTPUT |LVCMOS25 |4 |12 |SLOW |NONE** | | | | |NO |NONE |
|T13 | |DIFFM |IO_L01P_4/VRN_4 |UNUSED | |4 | | | | | | | | | |
|T14 |rs232_rxd |IOB |IO |INPUT |LVCMOS25 |4 | | | |IFD | | | |YES |NONE |
|T14 |sram1_io<10> |IOB |IO |BIDIR |LVCMOS25 |4 |12 |SLOW |NONE** |NONE | | | |NO |NONE |
|T15 | | |CCLK | | | | | | | | | | | | |
|T16 | | |GND | | | | | | | | | | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

2
xilinx/pdp8/top_prev_built.ngd
View File

File diff suppressed because one or more lines are too long

42
xilinx/pdp8/top_summary.html
View File

@@ -19,13 +19,13 @@
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc3s1000-5ft256</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/*.xmsgs'>47 Warnings</A></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/*.xmsgs'>48 Warnings</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD>
<TD>ISE 8.2i</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Updated:</B></LI></UL></TD>
<TD>Wed Apr 14 19:10:13 2010</TD>
<TD>Fri Apr 16 08:19:50 2010</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
@@ -38,52 +38,52 @@
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD>
<TD ALIGN=RIGHT>492</TD>
<TD ALIGN=RIGHT>519</TD>
<TD ALIGN=RIGHT>15,360</TD>
<TD ALIGN=RIGHT>3%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>
<TD ALIGN=RIGHT>1,374</TD>
<TD ALIGN=RIGHT>1,532</TD>
<TD ALIGN=RIGHT>15,360</TD>
<TD ALIGN=RIGHT>8%</TD>
<TD ALIGN=RIGHT>9%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Logic Distribution </B></TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>1,045</TD>
<TD ALIGN=RIGHT>1,135</TD>
<TD ALIGN=RIGHT>7,680</TD>
<TD ALIGN=RIGHT>13%</TD>
<TD ALIGN=RIGHT>14%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing only related logic</TD>
<TD ALIGN=RIGHT>1,045</TD>
<TD ALIGN=RIGHT>1,045</TD>
<TD ALIGN=RIGHT>1,135</TD>
<TD ALIGN=RIGHT>1,135</TD>
<TD ALIGN=RIGHT>100%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing unrelated logic</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1,045</TD>
<TD ALIGN=RIGHT>1,135</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total Number 4 input LUTs</B></TD>
<TD ALIGN=RIGHT>1,749</TD>
<TD ALIGN=RIGHT>1,884</TD>
<TD ALIGN=RIGHT>15,360</TD>
<TD ALIGN=RIGHT>11%</TD>
<TD ALIGN=RIGHT>12%</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number used as logic</TD>
<TD ALIGN=RIGHT>1,374</TD>
<TD ALIGN=RIGHT>1,532</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number used as a route-thru</TD>
<TD ALIGN=RIGHT>183</TD>
<TD ALIGN=RIGHT>160</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
@@ -113,7 +113,7 @@
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total equivalent gate count for design</B></TD>
<TD ALIGN=RIGHT>38,965</TD>
<TD ALIGN=RIGHT>40,005</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
@@ -150,12 +150,12 @@
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='6'><B>Detailed Reports</B></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Apr 14 19:03:14 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>37 Warnings</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>15 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed Apr 14 19:03:19 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed Apr 14 19:03:35 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>5 Warnings</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>3 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed Apr 14 19:04:46 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/par.xmsgs'>5 Warnings</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/par.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top.twr'>Static Timing Report</A></TD><TD>Current</TD><TD>Wed Apr 14 19:04:56 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/trce.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Wed Apr 14 19:10:11 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri Apr 16 08:15:48 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>36 Warnings</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>15 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri Apr 16 08:15:54 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Fri Apr 16 08:16:11 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>7 Warnings</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>3 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Fri Apr 16 08:17:42 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/par.xmsgs'>5 Warnings</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/par.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top.twr'>Static Timing Report</A></TD><TD>Current</TD><TD>Fri Apr 16 08:17:51 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/trce.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='top.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Fri Apr 16 08:19:47 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='3'><B>Secondary Reports</B></TD></TR>

760
xilinx/pdp8/top_usage.xml
View File

@@ -4,82 +4,82 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="4">
<DesignStatistics TimeStamp="Wed Apr 14 19:10:12 2010"><group name="NetStatistics">
<item name="NumNets_Active" rev="4">
<attrib name="value" value="1923"/></item>
<item name="NumNets_Gnd" rev="4">
<DesignSummary rev="3">
<DesignStatistics TimeStamp="Fri Apr 16 08:19:48 2010"><group name="NetStatistics">
<item name="NumNets_Active" rev="3">
<attrib name="value" value="2133"/></item>
<item name="NumNets_Gnd" rev="3">
<attrib name="value" value="1"/></item>
<item name="NumNets_Vcc" rev="4">
<item name="NumNets_Vcc" rev="3">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="4">
<attrib name="value" value="496"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="4">
<attrib name="value" value="630"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="4">
<attrib name="value" value="4456"/></item>
<item name="NumNodesOfType_Active_DUMMY" rev="4">
<attrib name="value" value="5883"/></item>
<item name="NumNodesOfType_Active_DUMMYESC" rev="4">
<item name="NumNodesOfType_Active_CLKPIN" rev="3">
<attrib name="value" value="512"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="3">
<attrib name="value" value="657"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="3">
<attrib name="value" value="5273"/></item>
<item name="NumNodesOfType_Active_DUMMY" rev="3">
<attrib name="value" value="6404"/></item>
<item name="NumNodesOfType_Active_DUMMYESC" rev="3">
<attrib name="value" value="17"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="4">
<attrib name="value" value="110"/></item>
<item name="NumNodesOfType_Active_HFULLHEX" rev="4">
<attrib name="value" value="60"/></item>
<item name="NumNodesOfType_Active_HLONG" rev="4">
<attrib name="value" value="7"/></item>
<item name="NumNodesOfType_Active_HUNIHEX" rev="4">
<attrib name="value" value="300"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="4">
<attrib name="value" value="6652"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="4">
<item name="NumNodesOfType_Active_GLOBAL" rev="3">
<attrib name="value" value="119"/></item>
<item name="NumNodesOfType_Active_HFULLHEX" rev="3">
<attrib name="value" value="73"/></item>
<item name="NumNodesOfType_Active_HLONG" rev="3">
<attrib name="value" value="14"/></item>
<item name="NumNodesOfType_Active_HUNIHEX" rev="3">
<attrib name="value" value="453"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="3">
<attrib name="value" value="7213"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="3">
<attrib name="value" value="31"/></item>
<item name="NumNodesOfType_Active_OMUX" rev="4">
<attrib name="value" value="1853"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="4">
<attrib name="value" value="1804"/></item>
<item name="NumNodesOfType_Active_PREBXBY" rev="4">
<attrib name="value" value="1668"/></item>
<item name="NumNodesOfType_Active_VFULLHEX" rev="4">
<attrib name="value" value="233"/></item>
<item name="NumNodesOfType_Active_VLONG" rev="4">
<attrib name="value" value="54"/></item>
<item name="NumNodesOfType_Active_VUNIHEX" rev="4">
<attrib name="value" value="354"/></item>
<item name="NumNodesOfType_Gnd_DOUBLE" rev="4">
<item name="NumNodesOfType_Active_OMUX" rev="3">
<attrib name="value" value="1955"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="3">
<attrib name="value" value="2014"/></item>
<item name="NumNodesOfType_Active_PREBXBY" rev="3">
<attrib name="value" value="1897"/></item>
<item name="NumNodesOfType_Active_VFULLHEX" rev="3">
<attrib name="value" value="239"/></item>
<item name="NumNodesOfType_Active_VLONG" rev="3">
<attrib name="value" value="49"/></item>
<item name="NumNodesOfType_Active_VUNIHEX" rev="3">
<attrib name="value" value="376"/></item>
<item name="NumNodesOfType_Gnd_DOUBLE" rev="3">
<attrib name="value" value="4"/></item>
<item name="NumNodesOfType_Gnd_INPUT" rev="4">
<item name="NumNodesOfType_Gnd_INPUT" rev="3">
<attrib name="value" value="50"/></item>
<item name="NumNodesOfType_Gnd_OMUX" rev="4">
<attrib name="value" value="46"/></item>
<item name="NumNodesOfType_Gnd_OUTPUT" rev="4">
<attrib name="value" value="37"/></item>
<item name="NumNodesOfType_Gnd_PREBXBY" rev="4">
<attrib name="value" value="22"/></item>
<item name="NumNodesOfType_Gnd_OMUX" rev="3">
<attrib name="value" value="45"/></item>
<item name="NumNodesOfType_Gnd_OUTPUT" rev="3">
<attrib name="value" value="38"/></item>
<item name="NumNodesOfType_Gnd_PREBXBY" rev="3">
<attrib name="value" value="27"/></item>
</group>
<group name="MiscellaneousStatistics">
<item name="AVG_LUT_FAN_IN" rev="0">
<attrib name="value" value="3.578600"/></item>
<attrib name="value" value="3.564600"/></item>
<item name="AVG_SIG_FANOUT" rev="0">
<attrib name="value" value="2.980000"/></item>
<attrib name="value" value="2.880000"/></item>
<item name="FOUR_LOAD_SIG" rev="0">
<attrib name="value" value="27"/></item>
<attrib name="value" value="116"/></item>
<item name="LUT" rev="0">
<attrib name="value" value="1374"/></item>
<attrib name="value" value="1532"/></item>
<item name="MAX_SIG_FANOUT" rev="0">
<attrib name="value" value="441"/></item>
<attrib name="value" value="471"/></item>
<item name="PK_NUM_4_INPUT_LUTS" rev="0">
<attrib name="value" value="1374"/></item>
<attrib name="value" value="1532"/></item>
<item name="PK_NUM_4_INPUT_LUT_RTS" rev="0">
<attrib name="value" value="183"/></item>
<attrib name="value" value="160"/></item>
<item name="PK_NUM_BONDED_IOBS" rev="0">
<attrib name="value" value="89"/></item>
<item name="PK_NUM_CYINIT" rev="0">
<attrib name="value" value="123"/></item>
<attrib name="value" value="119"/></item>
<item name="PK_NUM_CYMUX" rev="0">
<attrib name="value" value="221"/></item>
<attrib name="value" value="215"/></item>
<item name="PK_NUM_EQUIV_GATES" rev="0">
<attrib name="value" value="38"/></item>
<attrib name="value" value="40"/></item>
<item name="PK_NUM_IOB_FFS" rev="0">
<attrib name="value" value="14"/></item>
<item name="PK_NUM_JTAG_GATES" rev="0">
@@ -87,488 +87,538 @@
<item name="PK_NUM_LUTLESS_IOB_FFS" rev="0">
<attrib name="value" value="14"/></item>
<item name="PK_NUM_LUTLESS_SLICE_FFS" rev="0">
<attrib name="value" value="206"/></item>
<attrib name="value" value="180"/></item>
<item name="PK_NUM_MULTANDS" rev="0">
<attrib name="value" value="19"/></item>
<item name="PK_NUM_MUXF5" rev="0">
<attrib name="value" value="133"/></item>
<attrib name="value" value="91"/></item>
<item name="PK_NUM_MUXF6" rev="0">
<attrib name="value" value="12"/></item>
<item name="PK_NUM_MUXFS" rev="0">
<attrib name="value" value="241"/></item>
<attrib name="value" value="199"/></item>
<item name="PK_NUM_RAM32S" rev="0">
<attrib name="value" value="96"/></item>
<item name="PK_NUM_SLICELS" rev="0">
<attrib name="value" value="949"/></item>
<attrib name="value" value="1039"/></item>
<item name="PK_NUM_SLICEMS" rev="0">
<attrib name="value" value="96"/></item>
<item name="PK_NUM_SLICES" rev="0">
<attrib name="value" value="1045"/></item>
<attrib name="value" value="1135"/></item>
<item name="PK_NUM_SLICE_FFS" rev="0">
<attrib name="value" value="492"/></item>
<attrib name="value" value="519"/></item>
<item name="PK_NUM_TOTAL_LUTLESS_REGISTERS" rev="0">
<attrib name="value" value="220"/></item>
<attrib name="value" value="194"/></item>
<item name="PK_NUM_XBZ_GCLKS" rev="0">
<attrib name="value" value="3"/></item>
<item name="PK_NUM_XOR" rev="0">
<attrib name="value" value="202"/></item>
<attrib name="value" value="196"/></item>
<item name="SINGLE_LOAD_SIG" rev="0">
<attrib name="value" value="1035"/></item>
<attrib name="value" value="1059"/></item>
<item name="THREE_LOAD_SIG" rev="0">
<attrib name="value" value="41"/></item>
<attrib name="value" value="46"/></item>
<item name="TWO_LOAD_SIG" rev="0">
<attrib name="value" value="112"/></item>
<attrib name="value" value="127"/></item>
</group>
</DesignStatistics>
<DeviceUsage TimeStamp="Wed Apr 14 19:10:12 2010"><group name="SiteSummary">
<item name="BUFGMUX" rev="4">
<DeviceUsage TimeStamp="Fri Apr 16 08:19:48 2010"><group name="SiteSummary">
<item name="BUFGMUX" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
<item name="BUFGMUX_GCLKMUX" rev="4">
<item name="BUFGMUX_GCLKMUX" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
<item name="BUFGMUX_GCLK_BUFFER" rev="4">
<item name="BUFGMUX_GCLK_BUFFER" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
<item name="IOB" rev="4">
<item name="IOB" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="89"/></item>
<item name="IOB_DELAY" rev="4">
<item name="IOB_DELAY" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="14"/></item>
<item name="IOB_IFF1" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="14"/></item>
<item name="IOB_INBUF" rev="4">
<item name="IOB_IFF1" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="13"/></item>
<item name="IOB_IFF2" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="IOB_INBUF" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="31"/></item>
<item name="IOB_OUTBUF" rev="4">
<item name="IOB_OUTBUF" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="82"/></item>
<item name="IOB_PAD" rev="4">
<item name="IOB_PAD" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="89"/></item>
<item name="SLICEL" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="949"/></item>
<item name="SLICEL_C1VDD" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="15"/></item>
<item name="SLICEL_CYMUXF" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="115"/></item>
<item name="SLICEL_CYMUXG" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="106"/></item>
<item name="SLICEL_F" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="781"/></item>
<item name="SLICEL_F5MUX" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="133"/></item>
<item name="SLICEL_F6MUX" rev="4">
<item name="SLICEL" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="1039"/></item>
<item name="SLICEL_C1VDD" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="14"/></item>
<item name="SLICEL_CYMUXF" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="113"/></item>
<item name="SLICEL_CYMUXG" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="102"/></item>
<item name="SLICEL_F" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="856"/></item>
<item name="SLICEL_F5MUX" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="91"/></item>
<item name="SLICEL_F6MUX" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="12"/></item>
<item name="SLICEL_FFX" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="226"/></item>
<item name="SLICEL_FFY" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="266"/></item>
<item name="SLICEL_G" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="785"/></item>
<item name="SLICEL_GNDF" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="94"/></item>
<item name="SLICEL_GNDG" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="100"/></item>
<item name="SLICEL_XORF" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="97"/></item>
<item name="SLICEL_XORG" rev="4">
<attrib name="total" value="1000000"/><attrib name="used" value="105"/></item>
<item name="SLICEM" rev="4">
<item name="SLICEL_FAND" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="10"/></item>
<item name="SLICEL_FFX" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="214"/></item>
<item name="SLICEL_FFY" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="305"/></item>
<item name="SLICEL_G" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="844"/></item>
<item name="SLICEL_GAND" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="9"/></item>
<item name="SLICEL_GNDF" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="83"/></item>
<item name="SLICEL_GNDG" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="87"/></item>
<item name="SLICEL_XORF" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="93"/></item>
<item name="SLICEL_XORG" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="103"/></item>
<item name="SLICEM" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="96"/></item>
<item name="SLICEM_F" rev="4">
<item name="SLICEM_F" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="96"/></item>
<item name="SLICEM_F5MUX" rev="4">
<item name="SLICEM_F5MUX" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="96"/></item>
<item name="SLICEM_G" rev="4">
<item name="SLICEM_G" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="96"/></item>
<item name="SLICEM_WSGEN" rev="4">
<item name="SLICEM_WSGEN" rev="3">
<attrib name="total" value="1000000"/><attrib name="used" value="96"/></item>
</group>
</DeviceUsage>
<ReportConfigData TimeStamp="Wed Apr 14 19:10:12 2010"><group name="SLICEM_F">
<item name="LUT_OR_MEM" rev="4">
<ReportConfigData TimeStamp="Fri Apr 16 08:19:48 2010"><group name="SLICEM_F">
<item name="LUT_OR_MEM" rev="3">
<attrib name="RAM" value="96"/></item>
</group>
<group name="SLICEM_G">
<item name="LUT_OR_MEM" rev="4">
<item name="LUT_OR_MEM" rev="3">
<attrib name="RAM" value="96"/></item>
</group>
<group name="IOB_IFF1">
<item name="IFF1_INIT_ATTR" rev="4">
<attrib name="INIT0" value="13"/><attrib name="INIT1" value="1"/></item>
<item name="IFF1_SR_ATTR" rev="4">
<attrib name="SRLOW" value="12"/><attrib name="SRHIGH" value="1"/></item>
<item name="IFFATTRBOX" rev="4">
<attrib name="ASYNC" value="1"/><attrib name="SYNC" value="12"/></item>
<item name="LATCH_OR_FF" rev="4">
<attrib name="FF" value="14"/></item>
<item name="IFF1_INIT_ATTR" rev="3">
<attrib name="INIT0" value="12"/><attrib name="INIT1" value="1"/></item>
<item name="IFF1_SR_ATTR" rev="3">
<attrib name="SRLOW" value="11"/><attrib name="SRHIGH" value="1"/></item>
<item name="IFFATTRBOX" rev="3">
<attrib name="ASYNC" value="1"/><attrib name="SYNC" value="11"/></item>
<item name="LATCH_OR_FF" rev="3">
<attrib name="FF" value="13"/></item>
</group>
<group name="IOB_IFF2">
<item name="IFF2_INIT_ATTR" rev="3">
<attrib name="INIT0" value="1"/></item>
<item name="IFF2_SR_ATTR" rev="3">
<attrib name="SRLOW" value="1"/></item>
<item name="IFFATTRBOX" rev="3">
<attrib name="SYNC" value="1"/></item>
<item name="LATCH_OR_FF" rev="3">
<attrib name="FF" value="1"/></item>
</group>
<group name="SLICEL_FFX">
<item name="FFX_INIT_ATTR" rev="4">
<attrib name="INIT0" value="216"/><attrib name="INIT1" value="10"/></item>
<item name="FFX_SR_ATTR" rev="4">
<attrib name="SRLOW" value="216"/><attrib name="SRHIGH" value="10"/></item>
<item name="LATCH_OR_FF" rev="4">
<attrib name="FF" value="226"/></item>
<item name="SYNC_ATTR" rev="4">
<attrib name="ASYNC" value="52"/><attrib name="SYNC" value="174"/></item>
<item name="FFX_INIT_ATTR" rev="3">
<attrib name="INIT0" value="204"/><attrib name="INIT1" value="10"/></item>
<item name="FFX_SR_ATTR" rev="3">
<attrib name="SRLOW" value="204"/><attrib name="SRHIGH" value="10"/></item>
<item name="LATCH_OR_FF" rev="3">
<attrib name="FF" value="214"/></item>
<item name="SYNC_ATTR" rev="3">
<attrib name="ASYNC" value="52"/><attrib name="SYNC" value="162"/></item>
</group>
<group name="SLICEL_FFY">
<item name="FFY_INIT_ATTR" rev="4">
<attrib name="INIT0" value="256"/><attrib name="INIT1" value="10"/></item>
<item name="FFY_SR_ATTR" rev="4">
<attrib name="SRLOW" value="256"/><attrib name="SRHIGH" value="10"/></item>
<item name="LATCH_OR_FF" rev="4">
<attrib name="FF" value="266"/></item>
<item name="SYNC_ATTR" rev="4">
<attrib name="ASYNC" value="69"/><attrib name="SYNC" value="197"/></item>
<item name="FFY_INIT_ATTR" rev="3">
<attrib name="INIT0" value="294"/><attrib name="INIT1" value="11"/></item>
<item name="FFY_SR_ATTR" rev="3">
<attrib name="SRLOW" value="294"/><attrib name="SRHIGH" value="11"/></item>
<item name="LATCH_OR_FF" rev="3">
<attrib name="FF" value="305"/></item>
<item name="SYNC_ATTR" rev="3">
<attrib name="ASYNC" value="66"/><attrib name="SYNC" value="239"/></item>
</group>
<group name="BUFGMUX_GCLKMUX">
<item name="DISABLE_ATTR" rev="4">
<item name="DISABLE_ATTR" rev="3">
<attrib name="LOW" value="3"/></item>
</group>
<group name="IOB_PAD">
<item name="DRIVEATTRBOX" rev="4">
<item name="DRIVEATTRBOX" rev="3">
<attrib name="12" value="82"/></item>
<item name="IOATTRBOX" rev="4">
<item name="IOATTRBOX" rev="3">
<attrib name="LVCMOS25" value="89"/></item>
<item name="SLEW" rev="4">
<item name="SLEW" rev="3">
<attrib name="SLOW" value="82"/></item>
</group>
</ReportConfigData>
<ReportPinData TimeStamp="Wed Apr 14 19:10:12 2010"><group name="SLICEL_CYMUXF">
<item name="0" rev="4">
<attrib name="value" value="115"/></item>
<item name="1" rev="4">
<attrib name="value" value="115"/></item>
<item name="OUT" rev="4">
<attrib name="value" value="115"/></item>
<item name="S0" rev="4">
<attrib name="value" value="115"/></item>
<ReportPinData TimeStamp="Fri Apr 16 08:19:48 2010"><group name="SLICEL_CYMUXF">
<item name="0" rev="3">
<attrib name="value" value="113"/></item>
<item name="1" rev="3">
<attrib name="value" value="113"/></item>
<item name="OUT" rev="3">
<attrib name="value" value="113"/></item>
<item name="S0" rev="3">
<attrib name="value" value="113"/></item>
</group>
<group name="SLICEL_CYMUXG">
<item name="0" rev="4">
<attrib name="value" value="106"/></item>
<item name="1" rev="4">
<attrib name="value" value="106"/></item>
<item name="OUT" rev="4">
<attrib name="value" value="106"/></item>
<item name="S0" rev="4">
<attrib name="value" value="106"/></item>
<item name="0" rev="3">
<attrib name="value" value="102"/></item>
<item name="1" rev="3">
<attrib name="value" value="102"/></item>
<item name="OUT" rev="3">
<attrib name="value" value="102"/></item>
<item name="S0" rev="3">
<attrib name="value" value="102"/></item>
</group>
<group name="SLICEM_F">
<item name="A1" rev="4">
<item name="A1" rev="3">
<attrib name="value" value="96"/></item>
<item name="A2" rev="4">
<item name="A2" rev="3">
<attrib name="value" value="96"/></item>
<item name="A3" rev="4">
<item name="A3" rev="3">
<attrib name="value" value="96"/></item>
<item name="A4" rev="4">
<item name="A4" rev="3">
<attrib name="value" value="96"/></item>
<item name="D" rev="4">
<item name="D" rev="3">
<attrib name="value" value="96"/></item>
<item name="DI" rev="4">
<item name="DI" rev="3">
<attrib name="value" value="96"/></item>
<item name="WF1" rev="4">
<item name="WF1" rev="3">
<attrib name="value" value="96"/></item>
<item name="WF2" rev="4">
<item name="WF2" rev="3">
<attrib name="value" value="96"/></item>
<item name="WF3" rev="4">
<item name="WF3" rev="3">
<attrib name="value" value="96"/></item>
<item name="WF4" rev="4">
<item name="WF4" rev="3">
<attrib name="value" value="96"/></item>
<item name="WS" rev="4">
<item name="WS" rev="3">
<attrib name="value" value="96"/></item>
</group>
<group name="SLICEM_G">
<item name="A1" rev="4">
<item name="A1" rev="3">
<attrib name="value" value="96"/></item>
<item name="A2" rev="4">
<item name="A2" rev="3">
<attrib name="value" value="96"/></item>
<item name="A3" rev="4">
<item name="A3" rev="3">
<attrib name="value" value="96"/></item>
<item name="A4" rev="4">
<item name="A4" rev="3">
<attrib name="value" value="96"/></item>
<item name="D" rev="4">
<item name="D" rev="3">
<attrib name="value" value="96"/></item>
<item name="DI" rev="4">
<item name="DI" rev="3">
<attrib name="value" value="96"/></item>
<item name="WG1" rev="4">
<item name="WG1" rev="3">
<attrib name="value" value="96"/></item>
<item name="WG2" rev="4">
<item name="WG2" rev="3">
<attrib name="value" value="96"/></item>
<item name="WG3" rev="4">
<item name="WG3" rev="3">
<attrib name="value" value="96"/></item>
<item name="WG4" rev="4">
<item name="WG4" rev="3">
<attrib name="value" value="96"/></item>
<item name="WS" rev="4">
<item name="WS" rev="3">
<attrib name="value" value="96"/></item>
</group>
<group name="BUFGMUX_GCLK_BUFFER">
<item name="IN" rev="4">
<item name="IN" rev="3">
<attrib name="value" value="3"/></item>
<item name="OUT" rev="4">
<item name="OUT" rev="3">
<attrib name="value" value="3"/></item>
</group>
<group name="SLICEL">
<item name="BX" rev="4">
<attrib name="value" value="221"/></item>
<item name="BY" rev="4">
<attrib name="value" value="215"/></item>
<item name="CE" rev="4">
<attrib name="value" value="114"/></item>
<item name="CIN" rev="4">
<attrib name="value" value="105"/></item>
<item name="CLK" rev="4">
<attrib name="value" value="386"/></item>
<item name="COUT" rev="4">
<attrib name="value" value="106"/></item>
<item name="F1" rev="4">
<attrib name="value" value="773"/></item>
<item name="F2" rev="4">
<attrib name="value" value="671"/></item>
<item name="F3" rev="4">
<attrib name="value" value="630"/></item>
<item name="F4" rev="4">
<attrib name="value" value="494"/></item>
<item name="F5" rev="4">
<item name="BX" rev="3">
<attrib name="value" value="206"/></item>
<item name="BY" rev="3">
<attrib name="value" value="274"/></item>
<item name="CE" rev="3">
<attrib name="value" value="123"/></item>
<item name="CIN" rev="3">
<attrib name="value" value="101"/></item>
<item name="CLK" rev="3">
<attrib name="value" value="402"/></item>
<item name="COUT" rev="3">
<attrib name="value" value="102"/></item>
<item name="F1" rev="3">
<attrib name="value" value="850"/></item>
<item name="F2" rev="3">
<attrib name="value" value="759"/></item>
<item name="F3" rev="3">
<attrib name="value" value="697"/></item>
<item name="F4" rev="3">
<attrib name="value" value="528"/></item>
<item name="F5" rev="3">
<attrib name="value" value="24"/></item>
<item name="FXINA" rev="4">
<item name="FXINA" rev="3">
<attrib name="value" value="12"/></item>
<item name="FXINB" rev="4">
<item name="FXINB" rev="3">
<attrib name="value" value="12"/></item>
<item name="G1" rev="4">
<attrib name="value" value="784"/></item>
<item name="G2" rev="4">
<attrib name="value" value="689"/></item>
<item name="G3" rev="4">
<attrib name="value" value="589"/></item>
<item name="G4" rev="4">
<attrib name="value" value="470"/></item>
<item name="SR" rev="4">
<attrib name="value" value="363"/></item>
<item name="X" rev="4">
<attrib name="value" value="586"/></item>
<item name="XB" rev="4">
<item name="G1" rev="3">
<attrib name="value" value="842"/></item>
<item name="G2" rev="3">
<attrib name="value" value="760"/></item>
<item name="G3" rev="3">
<attrib name="value" value="662"/></item>
<item name="G4" rev="3">
<attrib name="value" value="523"/></item>
<item name="SR" rev="3">
<attrib name="value" value="381"/></item>
<item name="X" rev="3">
<attrib name="value" value="702"/></item>
<item name="XB" rev="3">
<attrib name="value" value="1"/></item>
<item name="XQ" rev="4">
<attrib name="value" value="226"/></item>
<item name="Y" rev="4">
<attrib name="value" value="495"/></item>
<item name="YQ" rev="4">
<attrib name="value" value="266"/></item>
<item name="XQ" rev="3">
<attrib name="value" value="214"/></item>
<item name="Y" rev="3">
<attrib name="value" value="566"/></item>
<item name="YQ" rev="3">
<attrib name="value" value="305"/></item>
</group>
<group name="SLICEM">
<item name="BX" rev="4">
<item name="BX" rev="3">
<attrib name="value" value="96"/></item>
<item name="BY" rev="4">
<item name="BY" rev="3">
<attrib name="value" value="96"/></item>
<item name="CLK" rev="4">
<item name="CLK" rev="3">
<attrib name="value" value="96"/></item>
<item name="F1" rev="4">
<item name="F1" rev="3">
<attrib name="value" value="96"/></item>
<item name="F2" rev="4">
<item name="F2" rev="3">
<attrib name="value" value="96"/></item>
<item name="F3" rev="4">
<item name="F3" rev="3">
<attrib name="value" value="96"/></item>
<item name="F4" rev="4">
<item name="F4" rev="3">
<attrib name="value" value="96"/></item>
<item name="G1" rev="4">
<item name="G1" rev="3">
<attrib name="value" value="96"/></item>
<item name="G2" rev="4">
<item name="G2" rev="3">
<attrib name="value" value="96"/></item>
<item name="G3" rev="4">
<item name="G3" rev="3">
<attrib name="value" value="96"/></item>
<item name="G4" rev="4">
<item name="G4" rev="3">
<attrib name="value" value="96"/></item>
<item name="SR" rev="4">
<item name="SR" rev="3">
<attrib name="value" value="96"/></item>
<item name="X" rev="4">
<item name="X" rev="3">
<attrib name="value" value="96"/></item>
</group>
<group name="SLICEL_F6MUX">
<item name="0" rev="4">
<item name="0" rev="3">
<attrib name="value" value="12"/></item>
<item name="1" rev="4">
<item name="1" rev="3">
<attrib name="value" value="12"/></item>
<item name="OUT" rev="4">
<item name="OUT" rev="3">
<attrib name="value" value="12"/></item>
<item name="S0" rev="4">
<item name="S0" rev="3">
<attrib name="value" value="12"/></item>
</group>
<group name="IOB_OUTBUF">
<item name="IN" rev="4">
<item name="IN" rev="3">
<attrib name="value" value="82"/></item>
<item name="OUT" rev="4">
<item name="OUT" rev="3">
<attrib name="value" value="82"/></item>
<item name="TRI" rev="4">
<item name="TRI" rev="3">
<attrib name="value" value="32"/></item>
</group>
<group name="IOB_IFF1">
<item name="CE" rev="4">
<attrib name="value" value="12"/></item>
<item name="CK" rev="4">
<attrib name="value" value="14"/></item>
<item name="D" rev="4">
<attrib name="value" value="14"/></item>
<item name="Q" rev="4">
<attrib name="value" value="14"/></item>
<item name="SR" rev="4">
<item name="CE" rev="3">
<attrib name="value" value="11"/></item>
<item name="CK" rev="3">
<attrib name="value" value="13"/></item>
<item name="D" rev="3">
<attrib name="value" value="13"/></item>
<item name="Q" rev="3">
<attrib name="value" value="13"/></item>
<item name="SR" rev="3">
<attrib name="value" value="12"/></item>
</group>
<group name="IOB_IFF2">
<item name="CE" rev="3">
<attrib name="value" value="1"/></item>
<item name="CK" rev="3">
<attrib name="value" value="1"/></item>
<item name="D" rev="3">
<attrib name="value" value="1"/></item>
<item name="Q" rev="3">
<attrib name="value" value="1"/></item>
<item name="SR" rev="3">
<attrib name="value" value="1"/></item>
</group>
<group name="IOB_DELAY">
<item name="IN" rev="4">
<item name="IN" rev="3">
<attrib name="value" value="14"/></item>
<item name="OUT" rev="4">
<item name="OUT" rev="3">
<attrib name="value" value="14"/></item>
</group>
<group name="SLICEM_F5MUX">
<item name="F" rev="4">
<item name="F" rev="3">
<attrib name="value" value="96"/></item>
<item name="G" rev="4">
<item name="G" rev="3">
<attrib name="value" value="96"/></item>
<item name="OUT" rev="4">
<item name="OUT" rev="3">
<attrib name="value" value="96"/></item>
<item name="S0" rev="4">
<item name="S0" rev="3">
<attrib name="value" value="96"/></item>
</group>
<group name="IOB_INBUF">
<item name="IN" rev="4">
<item name="IN" rev="3">
<attrib name="value" value="31"/></item>
<item name="OUT" rev="4">
<item name="OUT" rev="3">
<attrib name="value" value="31"/></item>
</group>
<group name="SLICEL_XORF">
<item name="0" rev="4">
<attrib name="value" value="97"/></item>
<item name="1" rev="4">
<attrib name="value" value="97"/></item>
<item name="O" rev="4">
<attrib name="value" value="97"/></item>
<item name="0" rev="3">
<attrib name="value" value="93"/></item>
<item name="1" rev="3">
<attrib name="value" value="93"/></item>
<item name="O" rev="3">
<attrib name="value" value="93"/></item>
</group>
<group name="SLICEL_FFX">
<item name="CE" rev="4">
<attrib name="value" value="59"/></item>
<item name="CK" rev="4">
<attrib name="value" value="226"/></item>
<item name="D" rev="4">
<attrib name="value" value="226"/></item>
<item name="Q" rev="4">
<attrib name="value" value="226"/></item>
<item name="REV" rev="4">
<attrib name="value" value="42"/></item>
<item name="SR" rev="4">
<attrib name="value" value="212"/></item>
<item name="CE" rev="3">
<attrib name="value" value="72"/></item>
<item name="CK" rev="3">
<attrib name="value" value="214"/></item>
<item name="D" rev="3">
<attrib name="value" value="214"/></item>
<item name="Q" rev="3">
<attrib name="value" value="214"/></item>
<item name="REV" rev="3">
<attrib name="value" value="70"/></item>
<item name="SR" rev="3">
<attrib name="value" value="200"/></item>
</group>
<group name="SLICEL_XORG">
<item name="0" rev="4">
<attrib name="value" value="105"/></item>
<item name="1" rev="4">
<attrib name="value" value="105"/></item>
<item name="O" rev="4">
<attrib name="value" value="105"/></item>
<item name="0" rev="3">
<attrib name="value" value="103"/></item>
<item name="1" rev="3">
<attrib name="value" value="103"/></item>
<item name="O" rev="3">
<attrib name="value" value="103"/></item>
</group>
<group name="SLICEL_FFY">
<item name="CE" rev="4">
<attrib name="value" value="101"/></item>
<item name="CK" rev="4">
<attrib name="value" value="266"/></item>
<item name="D" rev="4">
<attrib name="value" value="266"/></item>
<item name="Q" rev="4">
<attrib name="value" value="266"/></item>
<item name="REV" rev="4">
<attrib name="value" value="71"/></item>
<item name="SR" rev="4">
<attrib name="value" value="244"/></item>
<item name="CE" rev="3">
<attrib name="value" value="108"/></item>
<item name="CK" rev="3">
<attrib name="value" value="305"/></item>
<item name="D" rev="3">
<attrib name="value" value="305"/></item>
<item name="Q" rev="3">
<attrib name="value" value="305"/></item>
<item name="REV" rev="3">
<attrib name="value" value="97"/></item>
<item name="SR" rev="3">
<attrib name="value" value="286"/></item>
</group>
<group name="BUFGMUX_GCLKMUX">
<item name="I0" rev="4">
<item name="I0" rev="3">
<attrib name="value" value="3"/></item>
<item name="OUT" rev="4">
<item name="OUT" rev="3">
<attrib name="value" value="3"/></item>
<item name="S" rev="4">
<item name="S" rev="3">
<attrib name="value" value="3"/></item>
</group>
<group name="SLICEL_F5MUX">
<item name="F" rev="4">
<attrib name="value" value="133"/></item>
<item name="G" rev="4">
<attrib name="value" value="133"/></item>
<item name="OUT" rev="4">
<attrib name="value" value="133"/></item>
<item name="S0" rev="4">
<attrib name="value" value="133"/></item>
<item name="F" rev="3">
<attrib name="value" value="91"/></item>
<item name="G" rev="3">
<attrib name="value" value="91"/></item>
<item name="OUT" rev="3">
<attrib name="value" value="91"/></item>
<item name="S0" rev="3">
<attrib name="value" value="91"/></item>
</group>
<group name="SLICEL_GAND">
<item name="0" rev="3">
<attrib name="value" value="9"/></item>
<item name="1" rev="3">
<attrib name="value" value="9"/></item>
<item name="O" rev="3">
<attrib name="value" value="9"/></item>
</group>
<group name="SLICEM_WSGEN">
<item name="CK" rev="4">
<item name="CK" rev="3">
<attrib name="value" value="96"/></item>
<item name="WE" rev="4">
<item name="WE" rev="3">
<attrib name="value" value="96"/></item>
<item name="WE0" rev="4">
<item name="WE0" rev="3">
<attrib name="value" value="96"/></item>
<item name="WSF" rev="4">
<item name="WSF" rev="3">
<attrib name="value" value="96"/></item>
<item name="WSG" rev="4">
<item name="WSG" rev="3">
<attrib name="value" value="96"/></item>
</group>
<group name="IOB_PAD">
<item name="PAD" rev="4">
<item name="PAD" rev="3">
<attrib name="value" value="89"/></item>
</group>
<group name="SLICEL_C1VDD">
<item name="1" rev="4">
<attrib name="value" value="15"/></item>
<item name="1" rev="3">
<attrib name="value" value="14"/></item>
</group>
<group name="IOB">
<item name="I" rev="4">
<item name="I" rev="3">
<attrib name="value" value="17"/></item>
<item name="ICE" rev="4">
<item name="ICE" rev="3">
<attrib name="value" value="12"/></item>
<item name="ICLK1" rev="4">
<attrib name="value" value="14"/></item>
<item name="IQ1" rev="4">
<attrib name="value" value="14"/></item>
<item name="O1" rev="4">
<attrib name="value" value="82"/></item>
<item name="PAD" rev="4">
<attrib name="value" value="89"/></item>
<item name="SR" rev="4">
<item name="ICLK1" rev="3">
<attrib name="value" value="13"/></item>
<item name="T1" rev="4">
<item name="ICLK2" rev="3">
<attrib name="value" value="1"/></item>
<item name="IQ1" rev="3">
<attrib name="value" value="13"/></item>
<item name="IQ2" rev="3">
<attrib name="value" value="1"/></item>
<item name="O1" rev="3">
<attrib name="value" value="82"/></item>
<item name="PAD" rev="3">
<attrib name="value" value="89"/></item>
<item name="SR" rev="3">
<attrib name="value" value="13"/></item>
<item name="T1" rev="3">
<attrib name="value" value="32"/></item>
</group>
<group name="BUFGMUX">
<item name="I0" rev="4">
<item name="I0" rev="3">
<attrib name="value" value="3"/></item>
<item name="O" rev="4">
<item name="O" rev="3">
<attrib name="value" value="3"/></item>
<item name="S" rev="4">
<item name="S" rev="3">
<attrib name="value" value="3"/></item>
</group>
<group name="SLICEL_FAND">
<item name="0" rev="3">
<attrib name="value" value="10"/></item>
<item name="1" rev="3">
<attrib name="value" value="10"/></item>
<item name="O" rev="3">
<attrib name="value" value="10"/></item>
</group>
<group name="SLICEL_F">
<item name="A1" rev="4">
<attrib name="value" value="773"/></item>
<item name="A2" rev="4">
<attrib name="value" value="671"/></item>
<item name="A3" rev="4">
<attrib name="value" value="630"/></item>
<item name="A4" rev="4">
<attrib name="value" value="494"/></item>
<item name="D" rev="4">
<attrib name="value" value="781"/></item>
<item name="A1" rev="3">
<attrib name="value" value="850"/></item>
<item name="A2" rev="3">
<attrib name="value" value="759"/></item>
<item name="A3" rev="3">
<attrib name="value" value="697"/></item>
<item name="A4" rev="3">
<attrib name="value" value="528"/></item>
<item name="D" rev="3">
<attrib name="value" value="856"/></item>
</group>
<group name="SLICEL_G">
<item name="A1" rev="4">
<attrib name="value" value="784"/></item>
<item name="A2" rev="4">
<attrib name="value" value="689"/></item>
<item name="A3" rev="4">
<attrib name="value" value="589"/></item>
<item name="A4" rev="4">
<attrib name="value" value="470"/></item>
<item name="D" rev="4">
<attrib name="value" value="785"/></item>
<item name="A1" rev="3">
<attrib name="value" value="842"/></item>
<item name="A2" rev="3">
<attrib name="value" value="760"/></item>
<item name="A3" rev="3">
<attrib name="value" value="662"/></item>
<item name="A4" rev="3">
<attrib name="value" value="523"/></item>
<item name="D" rev="3">
<attrib name="value" value="844"/></item>
</group>
<group name="SLICEL_GNDF">
<item name="0" rev="4">
<attrib name="value" value="94"/></item>
<item name="0" rev="3">
<attrib name="value" value="83"/></item>
</group>
<group name="SLICEL_GNDG">
<item name="0" rev="4">
<attrib name="value" value="100"/></item>
<item name="0" rev="3">
<attrib name="value" value="87"/></item>
</group>
</ReportPinData>
<CmdHistory>

27
xilinx/pdp8/xst/work/hdllib.ref
View File

@@ -1,14 +1,13 @@
MO ide_disk NULL ../../rtl/ide_disk.v vlg10/ide__disk.bin 1271286113
MO pdp8_io NULL ../../rtl/pdp8_io.v vlg2F/pdp8__io.bin 1271286113
MO brg NULL ../../rtl/brg.v vlg33/brg.bin 1271286113
MO pdp8_kw NULL ../../rtl/pdp8_kw.v vlg41/pdp8__kw.bin 1271286113
MO pdp8_rf NULL ../../rtl/pdp8_rf.v vlg53/pdp8__rf.bin 1271286113
MO ram_32kx12 NULL ../../rtl/ram_32kx12.v vlg7A/ram__32kx12.bin 1271272061
MO pdp8_tt NULL ../../rtl/pdp8_tt.v vlg6B/pdp8__tt.bin 1271286113
MO debounce NULL ../../rtl/debounce.v vlg1D/debounce.bin 1271286113
MO top NULL ../../rtl/top.v vlg6F/top.bin 1271286113
MO ram_256x12 NULL ../../rtl/ram_256x12.v vlg37/ram__256x12.bin 1271286113
MO pdp8 NULL ../../rtl/pdp8.v vlg5C/pdp8.bin 1271286113
MO ide NULL ../../rtl/ide.v vlg1A/ide.bin 1271286113
MO pdp8_ram NULL ../../rtl/pdp8_ram.v vlg73/pdp8__ram.bin 1271286113
MO uart NULL ../../rtl/uart.v vlg48/uart.bin 1271286113
MO ide_disk NULL ../../rtl/ide_disk.v vlg10/ide__disk.bin 1271420062
MO pdp8_io NULL ../../rtl/pdp8_io.v vlg2F/pdp8__io.bin 1271420062
MO brg NULL ../../rtl/brg.v vlg33/brg.bin 1271420062
MO pdp8_kw NULL ../../rtl/pdp8_kw.v vlg41/pdp8__kw.bin 1271420062
MO pdp8_rf NULL ../../rtl/pdp8_rf.v vlg53/pdp8__rf.bin 1271420062
MO pdp8_tt NULL ../../rtl/pdp8_tt.v vlg6B/pdp8__tt.bin 1271420062
MO debounce NULL ../../rtl/debounce.v vlg1D/debounce.bin 1271420062
MO top NULL ../../rtl/top.v vlg6F/top.bin 1271420062
MO ram_256x12 NULL ../../rtl/ram_256x12.v vlg37/ram__256x12.bin 1271420061
MO pdp8 NULL ../../rtl/pdp8.v vlg5C/pdp8.bin 1271420062
MO ide NULL ../../rtl/ide.v vlg1A/ide.bin 1271420061
MO pdp8_ram NULL ../../rtl/pdp8_ram.v vlg73/pdp8__ram.bin 1271420062
MO uart NULL ../../rtl/uart.v vlg48/uart.bin 1271420061

BIN
xilinx/pdp8/xst/work/vlg1D/debounce.bin
View File

Binary file not shown.

BIN
xilinx/pdp8/xst/work/vlg2F/pdp8__io.bin
View File

Binary file not shown.

BIN
xilinx/pdp8/xst/work/vlg41/pdp8__kw.bin
View File

Binary file not shown.

BIN
xilinx/pdp8/xst/work/vlg53/pdp8__rf.bin
View File

Binary file not shown.

BIN
xilinx/pdp8/xst/work/vlg5C/pdp8.bin
View File

Binary file not shown.

BIN
xilinx/pdp8/xst/work/vlg6B/pdp8__tt.bin
View File

Binary file not shown.

BIN
xilinx/pdp8/xst/work/vlg6F/top.bin
View File

Binary file not shown.

BIN
xilinx/pdp8/xst/work/vlg73/pdp8__ram.bin
View File

Binary file not shown.