33 lines
1.8 KiB
XML
33 lines
1.8 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!-- IMPORTANT: This is an internal file that has been generated
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by the Xilinx ISE software. Any direct editing or
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changes made to this file may result in unpredictable
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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<messages>
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<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net ram_rd is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
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</msg>
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<msg type="warning" file="PhysDesignRules" num="367">The signal <slideswitch<4>_IBUF> is incomplete. The signal does not drive any load pins in the design.
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</msg>
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<msg type="warning" file="PhysDesignRules" num="367">The signal <slideswitch<5>_IBUF> is incomplete. The signal does not drive any load pins in the design.
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</msg>
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<msg type="warning" file="PhysDesignRules" num="367">The signal <slideswitch<6>_IBUF> is incomplete. The signal does not drive any load pins in the design.
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</msg>
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<msg type="warning" file="PhysDesignRules" num="367">The signal <slideswitch<7>_IBUF> is incomplete. The signal does not drive any load pins in the design.
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</msg>
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<msg type="warning" file="PhysDesignRules" num="367">The signal <button<0>_IBUF> is incomplete. The signal does not drive any load pins in the design.
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</msg>
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<msg type="warning" file="PhysDesignRules" num="367">The signal <button<1>_IBUF> is incomplete. The signal does not drive any load pins in the design.
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</msg>
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<msg type="warning" file="PhysDesignRules" num="367">The signal <button<2>_IBUF> is incomplete. The signal does not drive any load pins in the design.
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</msg>
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</messages>
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