31 lines
1.6 KiB
XML
31 lines
1.6 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!-- IMPORTANT: This is an internal file that has been generated
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by the Xilinx ISE software. Any direct editing or
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changes made to this file may result in unpredictable
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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<messages>
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<msg type="warning" file="LIT" num="243" delta="unknown" >Logical network <arg fmt="%s" index="1">clkb</arg> has no load.
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</msg>
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<msg type="warning" file="LIT" num="395" delta="unknown" >The above <arg fmt="%s" index="1">warning</arg> message <arg fmt="%s" index="2">base_net_load_rule</arg> is repeated <arg fmt="%d" index="3">11</arg> more times for the following (max. 5 shown):
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<arg fmt="%s" index="4">vga_hsync_n,
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vga_red0,
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vga_red1,
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vga_red2,
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vga_green0</arg>
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To see the details of these <arg fmt="%s" index="5">warning</arg> messages, please use the -detail switch.
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</msg>
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<msg type="info" file="MapLib" num="562" delta="unknown" >No environment variables are currently set.
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</msg>
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<msg type="info" file="LIT" num="244" delta="unknown" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.
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</msg>
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<msg type="warning" file="LIT" num="176" delta="unknown" >Clock buffer is designated to drive clock loads. <arg fmt="%s" index="1">BUFG symbol "gray_cnt_FFd1_BUFG" (output signal=gray_cnt_FFd1)</arg> has a mix of clock and non-clock loads. The non-clock loads are:
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<arg fmt="%s" index="2">Pin D of gray_cnt_FFd2</arg>
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</msg>
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</messages>
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