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mirror of synced 2026-01-20 17:58:10 +00:00
Description
FPGA based PDP-8/i clone in verilog. Includes several TSS/8 sources and utiltities to build from source
65 MiB
Languages
Verilog 46.9%
C 39%
Roff 4.1%
C++ 3.4%
Module Management System 1.7%
Other 4.7%