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tuning for PCB 2019-12

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CPU20 diags in comments
This commit is contained in:
Joerg Hoppe
2019-12-08 17:58:28 +01:00
parent 8ec0638b7e
commit 1b90dd73f7
3 changed files with 26 additions and 9 deletions
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6
10.01_base/2_src/pru1/pru1_statemachine_arbitration.c
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@@ -189,8 +189,8 @@ uint8_t sm_arb_worker_device(uint8_t granted_requests_mask) {
// "A device may not accept a grant (assert SACK) after it passes the grant"
uint8_t device_grant_mask = granted_requests_mask & sm_arb.device_request_mask & ~sm_arb.device_forwarded_grant_mask;
if (device_grant_mask) {
// one of our requests was granted: set SACK
// AND simultaneously clear granted requests BR*/NPR
// one of our requests was granted and not forwarded:
// set SACK AND simultaneously clear granted requests BR*/NPR
// BIT(5): SACK mask and level
buslatches_setbits(1, (PRIORITY_ARBITRATION_BIT_MASK & sm_arb.device_request_mask) | BIT(5),
~device_grant_mask | BIT(5))
@@ -207,7 +207,7 @@ uint8_t sm_arb_worker_device(uint8_t granted_requests_mask) {
}
return 0; // no REQUEST, or no GRANT for us, or wait for BG/BPG & BBSY && SSYN
} else {
// State 2: wait for BG/NPG, BBSY and SSYN to clear
// State 2: got GRANT, wait for BG/NPG, BBSY and SSYN to clear
// DMA and INTR:
// "After receiving the negation of BBSY, SSYN and BGn,
// the requesting device asserts BBSY"

8
10.01_base/2_src/pru1/pru1_timeouts.c
View File

@@ -96,18 +96,20 @@ void timeout_cleanup(uint32_t *target_cycles_var) {
// test a timeout, wether it reached its arg count nor or earlier
bool timeout_reached(uint32_t *target_cycles_var) {
bool result = false ;
// fast path: assume timeout_reached() is called
// because timeout is active
if (PRU1_CTRL.CYCLE < *target_cycles_var)
return false;
result = false;
else if (*target_cycles_var == 0)
return true; // already "reached" if inactive
result =true; // already "reached" if inactive
else {
// switched from "running" to "timeout reached"
*target_cycles_var = 0;
timeouts_active--;
return true;
result = true;
}
return result ;
}
void timeout_init(void) {

21
10.01_base/2_src/shared/tuning.h
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@@ -26,6 +26,7 @@
#define TUNING_PCB_LEGACY_SECURE
//#define TUNING_PCB_2018_12_OPTIMIZED
//#define TUNING_PCB_2019_12_OPTIMIZED
//#define TUNING_PCB_TEST
/*** Wait cycles for buslatch access. Depends on PCB, used chips and alofirth ***/
@@ -34,9 +35,9 @@
// #define BUSLATCHES_GETBYTE_DELAY 10 // Standard
#if defined(TUNING_PCB_TEST)
// experimental to test error rates
#define BUSLATCHES_GETBYTE_DELAY 10
#define BUSLATCHES_SETBITS_DELAY 4
#define BUSLATCHES_SETBYTE_DELAY 6
#define BUSLATCHES_GETBYTE_DELAY 7
#define BUSLATCHES_SETBITS_DELAY 0
#define BUSLATCHES_SETBYTE_DELAY 0
#elif defined(TUNING_PCB_LEGACY_SECURE)
/* Secure setting for PCBs <= 2018-12, delivered before June 2019.
@@ -71,6 +72,20 @@
//#define BUSLATCHES_GETBYTE_DELAY 8
//#define BUSLATCHES_SETBITS_DELAY 3
//#define BUSLATCHES_SETBYTE_DELAY 5
#elif defined(TUNING_PCB_2019_12_OPTIMIZED)
/* Setting for PCB v2018_12 with optimized timing (ticket 21, June 2019)
BeagleBone: BBB (no BBG)
U2 (REGSEL): 74AC138 -> 74AHC138
RN8,9 (DATIN) : 47 -> 68 Ohm
RN10 <1:6>(REGADR): 33->0 Ohm
RN10 <7:8>(REGWRITE): 33->0 Ohm
R6,R7 (REGWRITE TERM): none
RN6,RN7 (DATOUT inline): 22 -> 27
RN4,RN5 [[/DATOUT]] end) -> 180/-
*/
#define BUSLATCHES_GETBYTE_DELAY 7
#define BUSLATCHES_SETBITS_DELAY 0
#define BUSLATCHES_SETBYTE_DELAY 0
#endif
// UNIBUS timing: Wait to stabilize DATA before MSYN asserted