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Code Issues Releases Wiki Activity

module rename for upcoming intr_slave

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This commit is contained in:
Joerg Hoppe
2019-08-26 13:51:34 +02:00
parent ea91180f28
commit 827515eb8c
7 changed files with 32 additions and 32 deletions
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4
10.01_base/2_src/pru1/Makefile
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@@ -71,8 +71,8 @@ OBJECTS_COMMON= \
$(OBJ_DIR)/pru1_pru_mailbox.object \
$(OBJ_DIR)/pru1_statemachine_arbitration.object \
$(OBJ_DIR)/pru1_statemachine_dma.object \
$(OBJ_DIR)/pru1_statemachine_intr.object \
$(OBJ_DIR)/pru1_statemachine_slave.object \
$(OBJ_DIR)/pru1_statemachine_intr_master.object \
$(OBJ_DIR)/pru1_statemachine_data_slave.object \
$(OBJ_DIR)/pru1_timeouts.object \
$(OBJ_DIR)/pru1_utils.object

2
10.01_base/2_src/pru1/pru1_main_test.c
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@@ -53,7 +53,7 @@
#include "pru1_buslatches.h"
#include "pru1_statemachine_arbitration.h"
#include "pru1_statemachine_dma.h"
#include "pru1_statemachine_intr.h"
#include "pru1_statemachine_intr_master.h"
#include "pru1_statemachine_slave.h"
// Supress warnings about using void * as function pointers

10
10.01_base/2_src/pru1/pru1_main_unibus.c
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@@ -58,7 +58,7 @@
#include "pru1_buslatches.h"
#include "pru1_statemachine_arbitration.h"
#include "pru1_statemachine_dma.h"
#include "pru1_statemachine_intr.h"
#include "pru1_statemachine_intr_master.h"
#include "pru1_statemachine_slave.h"
// supress warnigns about using void * as function pointers
@@ -149,10 +149,10 @@ void main(void) {
uint8_t idx = PRIORITY_ARBITRATION_INTR_BIT2IDX(grant_mask);
// now transfer INTR vector for interupt of GRANted level.
// vector and ARM context have been setup by ARM before ARM2PRU_INTR already
sm_intr.vector = mailbox.intr.vector[idx];
sm_intr.level_index = idx; // to be returned to ARM on complete
sm_intr_master.vector = mailbox.intr.vector[idx];
sm_intr_master.level_index = idx; // to be returned to ARM on complete
sm_data_master_state = (statemachine_state_func) &sm_intr_start;
sm_data_master_state = (statemachine_state_func) &sm_intr_master_start;
}
}
} else {
@@ -224,7 +224,7 @@ void main(void) {
// by ARM, if access to "active" register triggers INTR.
sm_arb.request_mask |= mailbox.intr.priority_arbitration_bit;
// sm_arb_worker() evaluates this, extern Arbitrator raises Grant,
// vector of GRANted level is transfered with statemachine sm_intr
// vector of GRANted level is transfered with statemachine sm_intr_master
// Atomically change state in a device's associates interrupt register.
// The Interupt Register is set immediately. No wait for INTR GRANT,

0
10.01_base/2_src/pru1/pru1_statemachine_slave.c → 10.01_base/2_src/pru1/pru1_statemachine_data_slave.c
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0
10.01_base/2_src/pru1/pru1_statemachine_slave.h → 10.01_base/2_src/pru1/pru1_statemachine_data_slave.h
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34
10.01_base/2_src/pru1/pru1_statemachine_intr.c → 10.01_base/2_src/pru1/pru1_statemachine_intr_master.c
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@@ -1,6 +1,6 @@
/* pru1_statemachine_intr.c: state machine to transfer an interrupt vector
/* pru1_statemachine_intr_master.c: device transmits an interrupt vector after arb
Copyright (c) 2018, Joerg Hoppe
Copyright (c) 2018-2019, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Permission is hereby granted, free of charge, to any person obtaining a
@@ -41,29 +41,29 @@
#include "pru1_utils.h"
//#include "pru1_statemachine_arbitration.h"
#include "pru1_statemachine_intr.h"
#include "pru1_statemachine_intr_master.h"
// states
statemachine_intr_t sm_intr;
statemachine_intr_master_t sm_intr_master;
// forwards
static statemachine_state_func sm_intr_state_1(void);
static statemachine_state_func sm_intr_state_2(void);
static statemachine_state_func sm_intr_master_state_1(void);
static statemachine_state_func sm_intr_master_state_2(void);
// Wait for BBSY deasserted, then assert, SACK already held asserted
statemachine_state_func sm_intr_start() {
statemachine_state_func sm_intr_master_start() {
// Do not wait for BBSY here, this is part of Arbitration
// if (buslatches_getbyte(1) & BIT(6))
// return (statemachine_state_func) &sm_intr_start; // wait
// return (statemachine_state_func) &sm_intr_master_start; // wait
buslatches_setbits(1, BIT(6), BIT(6)); // assert BBSY
return (statemachine_state_func) &sm_intr_state_1;
return (statemachine_state_func) &sm_intr_master_state_1;
}
// place vector onto data, then set INTR
static statemachine_state_func sm_intr_state_1() {
static statemachine_state_func sm_intr_master_state_1() {
buslatches_setbyte(5, sm_intr.vector & 0xff); // DATA[0..7] = latch[5]
buslatches_setbyte(6, sm_intr.vector >> 8); // DATA[8..15] = latch[6]
buslatches_setbyte(5, sm_intr_master.vector & 0xff); // DATA[0..7] = latch[5]
buslatches_setbyte(6, sm_intr_master.vector >> 8); // DATA[8..15] = latch[6]
// set INTR
buslatches_setbits(7, BIT(0), BIT(0)); // INTR = latch 7, bit 0
@@ -74,20 +74,20 @@ static statemachine_state_func sm_intr_state_1() {
buslatches_setbits(1, BIT(5), 0); // SACK = latch[1], bit 5
// wait for processor to accept vector (no timeout?)
return (statemachine_state_func) &sm_intr_state_2;
return (statemachine_state_func) &sm_intr_master_state_2;
}
// wait for SSYN
static statemachine_state_func sm_intr_state_2() {
static statemachine_state_func sm_intr_master_state_2() {
if (!(buslatches_getbyte(4) & BIT(5)))
return (statemachine_state_func) &sm_intr_state_2; // wait
return (statemachine_state_func) &sm_intr_master_state_2; // wait
// received SSYN
// Complete and signal this INTR transaction only after ARM has processed the previous event.
// INTR may come faster than ARM Linux can process,
// especially if Arbitrator grants INTRs of multiple levels almost simultaneaously in parallel.
if (mailbox.events.event_intr)
return (statemachine_state_func) &sm_intr_state_2; // wait
return (statemachine_state_func) &sm_intr_master_state_2; // wait
// remove vector
buslatches_setbyte(5, 0); // DATA[0..7] = latch[5]
@@ -105,7 +105,7 @@ static statemachine_state_func sm_intr_state_2() {
// signal to ARM which INTR was completed
// change mailbox only after ARM has ack'ed mailbox.events.event_intr
mailbox.events.event_intr_level_index = sm_intr.level_index;
mailbox.events.event_intr_level_index = sm_intr_master.level_index;
mailbox.events.event_intr = 1;
// ARM is clearing this, before requesting new interrupt of same level
// so no concurrent ARP+PRU access

14
10.01_base/2_src/pru1/pru1_statemachine_intr.h → 10.01_base/2_src/pru1/pru1_statemachine_intr_master.h
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@@ -1,6 +1,6 @@
/* pru1_statemachine_intr.h: state machine to transfer an interrupt vector
/* pru1_statemachine_intr_master.h: device transmits an interrupt vector after arb
Copyright (c) 2018, Joerg Hoppe
Copyright (c) 2018-2019, Joerg Hoppe
j_hoppe@t-online.de, www.retrocmp.com
Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,18 +24,18 @@
29-jun-2019 JH rework: state returns ptr to next state func
12-nov-2018 JH entered beta phase
*/
#ifndef _PRU1_STATEMACHINE_INTR_H_
#define _PRU1_STATEMACHINE_INTR_H_
#ifndef _PRU1_STATEMACHINE_INTR_MASTER_H_
#define _PRU1_STATEMACHINE_INTR_MASTER_H_
#include "pru1_utils.h" // statemachine_state_func
typedef struct {
uint16_t vector; // interrupt vector to transfer
uint8_t level_index; // 0..3 = BR..BR7. to be returned to ARM on complete
} statemachine_intr_t;
} statemachine_intr_master_t;
extern statemachine_intr_t sm_intr;
extern statemachine_intr_master_t sm_intr_master;
statemachine_state_func sm_intr_start(void);
statemachine_state_func sm_intr_master_start(void);
#endif