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6f1b4767164c31a6798194e91ef8f51b2cb2b4de
livingcomputermuseum.UniBone/10.02_devices
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Josh Dersch 6f1b476716 Cleaned up signaling of DMA/INTR completion (using pthread_cond_wait). 
Tweaked MSYN timeout value from 350ns to 400ns to compensate for timing changes
with latest PRU code -- MSCP works reliably on PDP-11/84 again.
2019-08-16 02:23:32 +02:00
..
1_doc
Big summer rework:
2019-08-02 16:45:54 +02:00
2_src
Cleaned up signaling of DMA/INTR completion (using pthread_cond_wait).
2019-08-16 02:23:32 +02:00
3_test
Emulated DL11: stream interface parallel to RS232.
2019-08-10 10:19:05 +02:00
5_boot
Version 2019-06: many changes
2019-06-14 16:31:01 +02:00