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livingcomputermuseum.UniBone/10.01_base/2_src/pru1
History
Joerg Hoppe 1b90dd73f7 tuning for PCB 2019-12 
CPU20 diags in comments
2019-12-08 17:58:28 +01:00
..
AM335x_PRU.cmd
Initial
2019-04-05 11:30:26 +02:00
Makefile
CPU20 power start/power fail
2019-08-27 19:05:41 +02:00
pru1_arm_mailbox.c
Big summer rework:
2019-08-02 16:45:54 +02:00
pru1_buslatches.c
Test "MultiArb": parallel INTR and DMA of DL11,RL11,RK11.
2019-09-02 15:46:54 +02:00
pru1_buslatches.h
Big summer rework:
2019-08-02 16:45:54 +02:00
pru1_ddrmem.c
Big summer rework:
2019-08-02 16:45:54 +02:00
pru1_iopageregisters.c
Test "MultiArb": parallel INTR and DMA of DL11,RL11,RK11.
2019-09-02 15:46:54 +02:00
pru1_main_test.c
CPU20 UNIBUS Interrupt, Experiments to probe UNIBUS arbitrator
2019-10-08 12:36:36 +02:00
pru1_main_unibus.c
- Fix: got BBSY too early
2019-11-22 18:22:31 +01:00
pru1_pru_mailbox.c
Big summer rework:
2019-08-02 16:45:54 +02:00
pru1_statemachine_arbitration.c
tuning for PCB 2019-12
2019-12-08 17:58:28 +01:00
pru1_statemachine_arbitration.h
- Fix: got BBSY too early
2019-11-22 18:22:31 +01:00
pru1_statemachine_data_slave.c
PRU generated wrong GRANT OUT on REQUEST
2019-11-01 12:33:57 +01:00
pru1_statemachine_data_slave.h
CPU20 power start/power fail
2019-08-27 19:05:41 +02:00
pru1_statemachine_dma.c
CPU20 UNIBUS Interrupt, Experiments to probe UNIBUS arbitrator
2019-10-08 12:36:36 +02:00
pru1_statemachine_dma.h
CPU20 power start/power fail
2019-08-27 19:05:41 +02:00
pru1_statemachine_intr_master.c
DMA/INTR arbitration rework, emulated CPU20 with DMA&INTR, runs XXDP
2019-10-04 12:45:26 +02:00
pru1_statemachine_intr_master.h
module rename for upcoming intr_slave
2019-08-26 13:51:34 +02:00
pru1_statemachine_intr_slave.c
DMA/INTR arbitration rework, emulated CPU20 with DMA&INTR, runs XXDP
2019-10-04 12:45:26 +02:00
pru1_statemachine_intr_slave.h
CPU20 power start/power fail
2019-08-27 19:05:41 +02:00
pru1_timeouts.c
tuning for PCB 2019-12
2019-12-08 17:58:28 +01:00
pru1_timeouts.h
Test "MultiArb": parallel INTR and DMA of DL11,RL11,RK11.
2019-09-02 15:46:54 +02:00
pru1_utils.c
First successful iNTR on emulated CPU20
2019-09-23 13:42:47 +02:00
pru1_utils.h
Test "MultiArb": parallel INTR and DMA of DL11,RL11,RK11.
2019-09-02 15:46:54 +02:00
resource_table_empty.h
Initial
2019-04-05 11:30:26 +02:00