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PRU1 code split into multiple images 1. test functions 2. UNIBUS operation PRU1 bus latch interface Write byte/bits access not with MACROS (random optimizer influence), now with *_helper() procedures. Same timing, more determinism, much code saving. Nono more ASM code to write PRU0 XFER area. demo: menu to test UNIBUS signals directly rework "Arbitration" logic: now 3-fold Rework of UNIBUs arbtiration: NONE/CLIENT/MASTER - no Arbitrator (SACK penidng for 11/34 Konsole) (NONE) - phyiscal PDP_11 CPU is Arbitrator (CLIENT) - UniBone implements Arbitrator (MASTER) - Same PRU code loop handles all arbitration types PRU buslatch timing slower, for some problematic PCBs More aggressive bus latch selftest (mixed patterns, running on PRU now) Refinement of ready-to-run scripts - Adapted to changed "demo" menu - new name scheme <OS>_<boot- drive>_<PDP-11CPU> indicates - which OS is run - which disk emulation is used and what is the boot device - what is the (minimum) PDP-11 to run that Merged in Joshs DMA timing for 11/84 UNIBUS master cycles waits 350 us before MSYN, instead 150. Merged in Joshs DMA request queue multiple devices canrequest INTR and DMAs concurrently, will be put on the bus sequentially Merged in Joshs MSCP driver - Build RT-11v5.5 for MSCP - added boot loader "du.lst" MSCP run scrips 2.11BSD on MSCP on PDP-11/44 RT11 on MSCP Fix: image file sizing Disk image file exptend automatically if block beyond current file end is written
174 lines
4.3 KiB
C++
174 lines
4.3 KiB
C++
/* cpu.cpp: PDP-11/05 CPU
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Copyright (c) 2018, Angelo Papenhoff, Joerg Hoppe
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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23-nov-2018 JH created
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In worker() Angelos 11/05 CPU is running.
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Can do bus amster DAGTIDATO.
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*/
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#include <string.h>
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#include "mailbox.h"
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#include "unibus.h"
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#include "unibusadapter.hpp"
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#include "unibusdevice.hpp" // definition of class device_c
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#include "cpu.hpp"
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cpu_c::cpu_c() :
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unibusdevice_c() // super class constructor
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{
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// static config
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name.value = "CPU20";
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type_name.value = "PDP-11/20";
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log_label = "cpu";
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default_base_addr = 0; // none
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default_intr_vector = 0;
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default_intr_level = 0;
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// init parameters
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runmode.value = false;
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init.value = false;
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// current CPU does not publish registers to the bus
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register_count = 0;
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memset(&bus, 0, sizeof(bus)) ;
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memset(&ka11, 0, sizeof(ka11)) ;
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ka11.bus = &bus ;
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}
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cpu_c::~cpu_c() {
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}
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extern "C" {
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// functions to be used by Angelos CPU emulator
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// Result: 1 = OK, 0 = bus timeout
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int cpu_dato(unsigned addr, unsigned data) {
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bool timeout;
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mailbox->dma.words[0] = data;
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timeout = !unibus->dma(unibus_c::ARBITRATION_MODE_NONE, UNIBUS_CONTROL_DATO, addr, 1);
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return !timeout;
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}
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int cpu_datob(unsigned addr, unsigned data) {
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// TODO DATOB als 1 byte-DMA !
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bool timeout;
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mailbox->dma.words[0] = data;
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timeout = !unibus->dma(unibus_c::ARBITRATION_MODE_NONE, UNIBUS_CONTROL_DATOB, addr, 1);
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return !timeout;
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}
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int cpu_dati(unsigned addr, unsigned *data) {
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bool timeout;
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timeout = !unibus->dma(unibus_c::ARBITRATION_MODE_NONE, UNIBUS_CONTROL_DATI, addr, 1);
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*data = mailbox->dma.words[0];
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return !timeout;
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}
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}
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// background worker.
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// udpate LEDS, poll switches direct to register flipflops
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void cpu_c::worker(void) {
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timeout_c timeout;
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bool nxm;
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unsigned pc = 0;
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unsigned dr = 0760102;
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unsigned opcode = 0;
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(void) opcode;
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while (!worker_terminate) {
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timeout.wait_ms(10);
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if (runmode.value != (ka11.state != 0))
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ka11.state = runmode.value;
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condstep(&ka11);
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if (runmode.value != (ka11.state != 0))
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runmode.value = ka11.state != 0;
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if (init.value) {
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// user wants CPU reset
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reset(&ka11) ;
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init.value = 0 ;
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}
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#if 0
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if (runmode.value) {
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// simulate a fetch
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nxm = !cpu_dati(pc, &opcode);
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if (nxm) {
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printf("Bus timeout at PC = %06o. HALT.\n", pc);
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runmode.value = false;
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}
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pc = (pc + 2) % 0100; // loop around
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// set LEDS
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nxm = !cpu_dato(dr, pc & 0xf);
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if (nxm) {
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printf("Bus timeout at DR = %06o. HALT.\n", dr);
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runmode.value = false;
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}
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}
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#endif
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}
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}
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// process DATI/DATO access to one of my "active" registers
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// !! called asynchronuously by PRU, with SSYN asserted and blocking UNIBUS.
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// The time between PRU event and program flow into this callback
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// is determined by ARM Linux context switch
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//
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// UNIBUS DATO cycles let dati_flipflops "flicker" outside of this proc:
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// do not read back dati_flipflops.
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void cpu_c::on_after_register_access(unibusdevice_register_t *device_reg,
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uint8_t unibus_control) {
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// nothing todo
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UNUSED(device_reg);
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UNUSED(unibus_control);
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}
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bool cpu_c::on_param_changed(parameter_c *param) {
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UNUSED(param) ;
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return true ;
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}
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void cpu_c::on_power_changed(void) {
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if (power_down) { // power-on defaults
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}
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}
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// UNIBUS INIT: clear all registers
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void cpu_c::on_init_changed(void) {
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// write all registers to "reset-values"
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if (init_asserted) {
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reset_unibus_registers();
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INFO("demo_io_c::on_init()");
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}
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}
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