debugging - added ide to top

verif/fake_ide.v

@@ -0,0 +1,83 @@
+
+module fake_ide(ide_dior, ide_diow, ide_cs, ide_da, ide_data_bus);
+
+   input        ide_dior;
+   input        ide_diow;
+   input [1:0] 	ide_cs;
+   input [2:0] 	ide_da;
+   inout [15:0] ide_data_bus;
+
+   reg [7:0] 	data_out;
+   reg [7:0] 	cmd;
+   reg [7:0] 	status;
+   reg [7:0] 	drvhead;
+   
+   integer 	fifo;
+   
+   wire 	is_rd;
+   wire 	is_wr;
+
+   assign is_rd = ide_dior == 1'b0 && (ide_cs[0] == 1'b0 || ide_cs[1] == 1'b0);
+   assign is_wr = ide_diow == 1'b0 && (ide_cs[0] == 1'b0 || ide_cs[1] == 1'b0);
+   
+   assign ide_data_bus = is_rd ? data_out : 12'bz;
+
+   initial
+     begin
+	status = 8'h50;
+     end
+
+   always @(*)
+     begin
+	if (ide_dior == 1'b0 && (ide_cs[0] == 1'b0 || ide_cs[1] == 1'b0))
+	  begin
+	     if (ide_da != 0)
+	       #1 $display("ide r cs %b; da %b; bus %x",
+			   ide_cs, ide_da, ide_data_bus);
+	     case (ide_da)
+	       3'd0:
+		 begin
+		    if (fifo > 0)
+		      begin
+			 data_out = 0;
+			 fifo = fifo - 1;
+			 //$display("fifo %d", fifo);
+		      end
+		    if (fifo == 0)
+		      begin
+			 $display("ide empty!");
+			 status = 8'h50;
+			 cmd = 0;
+		      end			 
+		 end
+	       3'd7:
+		 data_out = status;
+	     endcase
+	     
+	  end
+	if (ide_diow == 1'b0 && (ide_cs[0] == 1'b0 || ide_cs[1] == 1'b0))
+	  begin
+	     #1 $display("ide w cs %b; da %b; bus %x",
+		      ide_cs, ide_da, ide_data_bus);
+	     case (ide_da)
+	       3'd6:
+		 drvhead = ide_data_bus;
+	       
+	       3'd7:
+		 begin
+		    //release ide_data_bus;
+		    cmd = ide_data_bus;
+		    #1 $display("ide cmd %x", cmd);
+		    case (cmd)
+		      8'h20:
+			begin
+			   status = 8'h58;
+			   fifo = 256;
+			end
+		    endcase
+		 end
+	     endcase
+	  end
+     end
+
+endmodule

verif/test_pdp8.v

@@ -7,6 +7,8 @@
 `include "../rtl/pdp8_io.v"
 `include "../rtl/pdp8_ram.v"
 `include "../rtl/pdp8.v"
+`include "../rtl/ide_disk.v"
+`include "../rtl/ide.v"
 `include "../rtl/ram_32kx12.v"
 `include "../rtl/ram_256x12.v"
 

verif/test_rf.v

@@ -3,7 +3,10 @@
 //
 
 `include "../rtl/pdp8_rf.v"
+`include "../rtl/ide_disk.v"
+`include "../rtl/ide.v"
 `include "../rtl/ram_256x12.v"
+`include "../verif/fake_ide.v"
 
 `timescale 1ns / 1ns
 
@@ -29,7 +32,19 @@ module test;
    reg 	       iot;
    reg [3:0]   state;
    reg [11:0]  mb_in;
-   
+
+   wire        ide_dior;
+   wire        ide_diow;
+   wire [1:0]  ide_cs;
+   wire [2:0]  ide_da;
+   wire [15:0] ide_data_bus;
+
+   fake_ide ide(.ide_dior(ide_dior),
+		.ide_diow(ide_diow),
+		.ide_cs(ide_cs),
+		.ide_da(ide_da),
+		.ide_data_bus(ide_data_bus));
+
    pdp8_rf rf(.clk(clk),
 	      .reset(reset),
 	      .iot(iot),
@@ -46,7 +61,12 @@ module test;
 	      .ram_done(ram_done),
 	      .ram_ma(ram_ma),
 	      .ram_in(ram_in),
-	      .ram_out(ram_out));
+	      .ram_out(ram_out),
+	      .ide_dior(ide_dior),
+	      .ide_diow(ide_diow),
+	      .ide_cs(ide_cs),
+	      .ide_da(ide_da),
+	      .ide_data_bus(ide_data_bus));
 
    //
    task write_rf_reg;
@@ -136,7 +156,7 @@ module test;
 	write_rf_reg(12'o6000, 12'o0000);
 	write_rf_reg(12'o6000, 12'o0000);
   
-	#3000 $finish;
+	#40000 $finish;
      end
 
   always