Add TX to top

interface2/rtl/pins.pcf

@@ -1,14 +1,24 @@
 # 16MHz clock
 set_io --warn-no-port clk_16mhz B2
 
+# Transmitter
+set_io --warn-no-port tx_active A2 # 1
+set_io --warn-no-port tx_inverted A1 # 2
+set_io --warn-no-port tx_delay B1 # 3
+
+set_io --warn-no-port tx_load D2 # 6
+set_io --warn-no-port tx_full D1 # 7
+
 # Receiver
-set_io --warn-no-port rx A2
-set_io --warn-no-port rx_active D2
-set_io --warn-no-port rx_data_available D1
-set_io --warn-no-port rx_data_read E2
+set_io --warn-no-port rx C2 # 4
+
+set_io --warn-no-port rx_enable E1 # 9
+set_io --warn-no-port rx_active G2 # 10
+set_io --warn-no-port rx_data_available H1 # 11
+set_io --warn-no-port rx_data_read J1 # 12
 
 # Shared data bus
-set_io --warn-no-port data[9] B6
+set_io --warn-no-port data[9] B6 # 23
 set_io --warn-no-port data[8] A7
 set_io --warn-no-port data[7] B7
 set_io --warn-no-port data[6] A8
@@ -17,6 +27,8 @@ set_io --warn-no-port data[4] A9
 set_io --warn-no-port data[3] C9
 set_io --warn-no-port data[2] D8
 set_io --warn-no-port data[1] D9
-set_io --warn-no-port data[0] H9
+set_io --warn-no-port data[0] H9 # 14
+
+set_io --warn-no-port debug H2 # 13
 
 set_io --warn-no-port usb_pu A3

interface2/rtl/top.v

@@ -3,7 +3,15 @@
 module top (
     input clk_16mhz,
 
+    // Transmitter
+    input tx_load,
+    output tx_full,
+    output tx_active,
+    output tx_delay,
+    output tx_inverted,
+
     // Receiver
+    input rx_enable,
     input rx,
     output rx_active,
     output rx_data_available,
@@ -12,6 +20,8 @@ module top (
     // Shared data bus
     inout [9:0] data,
 
+    output debug,
+
     output usb_pu
 );
     // 19 MHz
@@ -32,16 +42,38 @@ module top (
         .PLLOUTCORE(clk_19mhz)
     );
 
+    wire [9:0] tx_data;
+
+    assign tx_data = data;
+
+    coax_tx #(
+        .CLOCKS_PER_BIT(8)
+    ) coax_tx (
+        .clk(clk_19mhz),
+        .load(tx_load),
+        .data(tx_data),
+        .full(tx_full),
+        .active(tx_active),
+        .tx_delay(tx_delay),
+        .tx_inverted(tx_inverted)
+    );
+
+    wire [9:0] rx_data;
+
     coax_rx #(
         .CLOCKS_PER_BIT(8)
     ) coax_rx (
         .clk(clk_19mhz),
         .rx(rx),
         .active(rx_active),
-        .data(data),
+        .data(rx_data),
         .data_available(rx_data_available),
         .data_read(rx_data_read)
     );
 
+    assign data = rx_enable ? rx_data : 10'bzzzzzzzzzz;
+
+    assign debug = rx;
+
     assign usb_pu = 0;
 endmodule