Adding tx_inverted and updating pins

interface2/rtl/coax_tx.v

@@ -3,9 +3,10 @@
 module coax_tx (
     input clk,
     input xxx,
-    output reg tx, // ??? why does thie have to be reg?
     output active,
-    output tx_delay
+    output reg tx, // ??? why does thie have to be reg?
+    output tx_delay,
+    output tx_inverted
 );
     parameter CLOCKS_PER_BIT = 8;
 
@@ -116,6 +117,8 @@ module coax_tx (
             tx_delay_reg <= { tx_delay_reg[0], tx };
     end
 
+    assign active = ((state == LINE_QUIESCE_1 && !bit_first_half) || state > LINE_QUIESCE_1);
+
     always @(*) // ??? is this best?
     begin
         tx <= 0;
@@ -140,7 +143,6 @@ module coax_tx (
             tx <= 1;
     end
 
-    assign active = ((state == LINE_QUIESCE_1 && !bit_first_half) || state > LINE_QUIESCE_1);
-
     assign tx_delay = active ? tx_delay_reg[1] : 0;
+    assign tx_inverted = active ? ~tx : 0;
 endmodule

interface2/rtl/pins.pcf

@@ -1,5 +1,7 @@
-set_io --warn-no-port tx B8
-set_io --warn-no-port tx_active A9
+set_io --warn-no-port tx_active B1
+set_io --warn-no-port tx C2
+set_io --warn-no-port tx_delay C1
+set_io --warn-no-port tx_inverted D2
 
 # 16MHz clock
 set_io --warn-no-port clk_16mhz B2

interface2/rtl/top.v

@@ -2,8 +2,10 @@
 
 module top (
     input clk_16mhz,
-    output tx,
     output tx_active,
+    output tx,
+    output tx_delay,
+    output tx_inverted,
     output usb_pu
 );
     // 19 MHz
@@ -27,8 +29,10 @@ module top (
     coax_tx coax_tx (
         .clk(clk_19mhz),
         .xxx(do_it),
+        .active(tx_active),
         .tx(tx),
-        .active(tx_active)
+        .tx_delay(tx_delay),
+        .tx_inverted(tx_inverted)
     );
 
     wire do_it;