wip

interface2/rtl/coax_rx.v

@@ -0,0 +1,44 @@
+`default_nettype none
+
+module coax_rx (
+    input clk,
+    input rx,
+    input reset
+);
+    parameter CLOCKS_PER_BIT = 8;
+
+    localparam IDLE = 0;
+
+    reg [1:0] state = IDLE;
+    reg [1:0] next_state;
+
+    wire sample;
+    wire synchronized;
+
+    coax_rx_bit_timer #(
+        .CLOCKS_PER_BIT(CLOCKS_PER_BIT)
+    ) bit_timer (
+        .clk(clk),
+        .rx(rx),
+        .reset(reset),
+        .sample(sample),
+        .synchronized(synchronized)
+    );
+
+    always @(*)
+    begin
+        next_state = state;
+
+        case (state)
+            IDLE: next_state = synchronized && sample && rx ? 
+        endcase
+    end
+
+    always @(posedge clk)
+    begin
+        state <= next_state;
+
+        if (reset)
+            state <= IDLE;
+    end
+endmodule

interface2/tests/Makefile

@@ -3,9 +3,10 @@ VVP ?= vvp
 
 RTL = ../rtl
 
-all: coax_rx_bit_timer_tb.vcd
+all: coax_rx_bit_timer_tb.vcd coax_rx_tb.vcd
 
 coax_rx_bit_timer_tb: coax_rx_bit_timer_tb.v $(RTL)/coax_rx_bit_timer.v
+coax_rx_tb: coax_rx_tb.v $(RTL)/coax_rx.v $(RTL)/coax_rx_bit_timer.v
 
 clean:
 	rm -f *_tb *.vcd

interface2/tests/coax_rx_bit_timer_tb.v

@@ -1,6 +1,6 @@
 `default_nettype none
 
-module coax_rx_bit_timer_tb ();
+module coax_rx_bit_timer_tb;
     reg clk = 0;
 
     initial begin
@@ -46,9 +46,7 @@ module coax_rx_bit_timer_tb ();
         rx_bit_custom(1, 24, 8);
 
         // Reset
-        reset = 1;
-        #2;
-        reset = 0;
+        dut_reset;
 
         rx_bit(1);
 
@@ -57,6 +55,14 @@ module coax_rx_bit_timer_tb ();
         $finish;
     end
 
+    task dut_reset;
+    begin
+        reset = 1;
+        #2;
+        reset = 0;
+    end
+    endtask
+
     task rx_bit (
         input bit
     );

interface2/tests/coax_rx_tb.v

@@ -0,0 +1,110 @@
+`default_nettype none
+
+module coax_rx_tb;
+    reg clk = 0;
+
+    initial begin
+        forever begin
+            #1 clk <= ~clk;
+        end
+    end
+
+    reg rx = 0;
+    reg reset = 0;
+
+    coax_rx #(
+        .CLOCKS_PER_BIT(8)
+    ) dut (
+        .clk(clk),
+        .rx(rx),
+        .reset(reset)
+    );
+
+    initial begin
+        $dumpfile("coax_rx_tb.vcd");
+        $dumpvars(0, coax_rx_tb);
+
+        test_1;
+        test_2;
+
+        $finish;
+    end
+
+    task test_1;
+    begin
+        $display("START: test_1");
+
+        dut_reset;
+
+        #8;
+
+        $display("END: test_1");
+    end
+    endtask
+
+    task test_2;
+    begin
+        $display("START: test_2");
+
+        rx = 1;
+
+        #64;
+
+        $display("END: test_2");
+    end
+    endtask
+
+    task dut_reset;
+    begin
+        reset = 1;
+        #2;
+        reset = 0;
+    end
+    endtask
+
+    task rx_bit (
+        input bit
+    );
+    begin
+        rx_bit_custom(bit, 8, 8);
+    end
+    endtask
+
+    task rx_start_sequence;
+    begin
+        rx_bit(1);
+        rx_bit(1);
+        rx_bit(1);
+        rx_bit(1);
+        rx_bit(1);
+
+        rx = 0;
+        #24;
+        rx = 1;
+        #24;
+    end
+    endtask
+
+    task rx_end_sequence;
+    begin
+        rx_bit(0);
+
+        rx = 1;
+        #32;
+    end
+    endtask
+
+    task rx_bit_custom (
+        input bit,
+        input [15:0] first_half_duration,
+        input [15:0] second_half_duration
+    );
+    begin
+        rx = !bit;
+        #first_half_duration;
+        rx = bit;
+        #second_half_duration;
+        rx = 0;
+    end
+    endtask
+endmodule