testing rx_coax_bit_timer on TinyFPGA

interface2/firmware/.gitignore

@@ -0,0 +1 @@
+.pio

interface2/firmware/platformio.ini

@@ -0,0 +1,6 @@
+[env]
+framework = arduino
+
+[env:teensy40]
+platform = teensy
+board = teensy40

interface2/firmware/src/main.cpp

@@ -0,0 +1,59 @@
+#include <Arduino.h>
+
+#define RESET_PIN 2 // FPGA #9
+
+char buffer[20 + 1];
+int bufferIndex = 0;
+
+void doReset()
+{
+    Serial.println("RESET");
+
+    digitalWrite(RESET_PIN, HIGH);
+    digitalWrite(RESET_PIN, LOW);
+
+    Serial.println("OK");
+}
+
+void setup()
+{
+    pinMode(RESET_PIN, OUTPUT);
+
+    digitalWrite(RESET_PIN, LOW);
+
+    Serial.begin(115200);
+
+    while (Serial.available() > 0) {
+        Serial.read();
+    }
+
+    Serial.println("OK");
+}
+
+void loop()
+{
+    if (Serial.available() > 0) {
+        uint8_t byte = Serial.read();
+
+        if (byte == '\r') {
+            buffer[bufferIndex] = 0;
+
+            Serial.println();
+
+            if (strncmp(buffer, "reset", 20) == 0) {
+                doReset();
+            } else {
+                Serial.println("UNRECOGNIZED COMMAND");
+            }
+
+            Serial.flush();
+
+            bufferIndex = 0;
+        } else {
+            buffer[bufferIndex++] = byte;
+        }
+
+        Serial.write(byte);
+        Serial.flush();
+    }
+}

interface2/rtl/coax_rx_bit_timer.v

@@ -1,6 +1,6 @@
 `default_nettype none
 
-module coax_rx_bit_timer(
+module coax_rx_bit_timer (
     input clk,
     input rx,
     input reset,

interface2/rtl/pins.pcf

@@ -2,32 +2,36 @@
 set_io --warn-no-port clk_16mhz B2
 
 # Transmitter
-set_io --warn-no-port tx_active A2 # 1
-set_io --warn-no-port tx_inverted A1 # 2
-set_io --warn-no-port tx_delay B1 # 3
+#set_io --warn-no-port tx_active A2 # 1
+#set_io --warn-no-port tx_inverted A1 # 2
+#set_io --warn-no-port tx_delay B1 # 3
 
-set_io --warn-no-port tx_load D2 # 6
-set_io --warn-no-port tx_full D1 # 7
+#set_io --warn-no-port tx_load D2 # 6
+#set_io --warn-no-port tx_full D1 # 7
 
 # Receiver
 set_io --warn-no-port rx C2 # 4
 
-set_io --warn-no-port rx_enable E1 # 9
-set_io --warn-no-port rx_active G2 # 10
-set_io --warn-no-port rx_data_available H1 # 11
-set_io --warn-no-port rx_data_read J1 # 12
+set_io --warn-no-port reset E1 # 9
+set_io --warn-no-port sample G2 # 10
+set_io --warn-no-port synchronized H1 # 11
+
+#set_io --warn-no-port rx_enable E1 # 9
+#set_io --warn-no-port rx_active G2 # 10
+#set_io --warn-no-port rx_data_available H1 # 11
+#set_io --warn-no-port rx_data_read J1 # 12
 
 # Shared data bus
-set_io --warn-no-port data[9] B6 # 23
-set_io --warn-no-port data[8] A7
-set_io --warn-no-port data[7] B7
-set_io --warn-no-port data[6] A8
-set_io --warn-no-port data[5] B8
-set_io --warn-no-port data[4] A9
-set_io --warn-no-port data[3] C9
-set_io --warn-no-port data[2] D8
-set_io --warn-no-port data[1] D9
-set_io --warn-no-port data[0] H9 # 14
+#set_io --warn-no-port data[9] B6 # 23
+#set_io --warn-no-port data[8] A7
+#set_io --warn-no-port data[7] B7
+#set_io --warn-no-port data[6] A8
+#set_io --warn-no-port data[5] B8
+#set_io --warn-no-port data[4] A9
+#set_io --warn-no-port data[3] C9
+#set_io --warn-no-port data[2] D8
+#set_io --warn-no-port data[1] D9
+#set_io --warn-no-port data[0] H9 # 14
 
 set_io --warn-no-port debug H2 # 13
 

interface2/rtl/top.v

@@ -9,6 +9,7 @@ module top (
     input reset,
     output sample,
     output synchronized,
+    output debug,
 
     output usb_pu
 );
@@ -49,5 +50,7 @@ module top (
         .synchronized(synchronized)
     );
 
+    assign debug = rx_1;
+
     assign usb_pu = 0;
 endmodule

interface2/tests/coax_rx_bit_timer_tb.v

@@ -1,6 +1,6 @@
 `default_nettype none
 
-module coax_rx_bit_timer_tb();
+module coax_rx_bit_timer_tb ();
     reg clk = 0;
 
     initial begin
@@ -61,11 +61,7 @@ module coax_rx_bit_timer_tb();
         input bit
     );
     begin
-        rx = !bit;
-        #8;
-        rx = bit;
-        #8;
-        rx = 0;
+        rx_bit_custom(bit, 8, 8);
     end
     endtask
 

interface2/tests/coax_rx_bit_timer_tb.vcd_snapshot

@@ -1,5 +1,5 @@
 $date
-	Mon Jun 15 21:59:45 2020
+	Sun Jun 21 18:50:14 2020
 $end
 $version
 	Icarus Verilog
@@ -121,6 +121,9 @@ $end
 1#
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@@ -183,6 +186,7 @@ b11 ,
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@@ -264,6 +268,7 @@ b11 ,
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@@ -347,7 +352,6 @@ b11 ,
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@@ -441,15 +445,44 @@ b110 /
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@@ -457,44 +490,15 @@ b11 )
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@@ -502,133 +506,141 @@ b1000 0
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