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This commit is contained in:
Andrew Kay
2020-06-16 16:53:53 -05:00
parent 0a03fde6f9
commit 9dd8d37ef5
4 changed files with 863 additions and 5 deletions
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2
interface2/rtl/Makefile
View File

@@ -5,7 +5,7 @@ TINYPROG ?= tinyprog
all: top.bin
top.json: top.v
top.json: top.v coax_rx_bit_timer.v
prog: top.bin
$(TINYPROG) -p top.bin

8
interface2/rtl/coax_rx_bit_timer.v
View File

@@ -47,7 +47,7 @@ module coax_rx_bit_timer(
SYNCHRONIZED:
begin
if (transition_counter < CLOCKS_PER_BIT * 1.25)
if (transition_counter < (CLOCKS_PER_BIT + (CLOCKS_PER_BIT / 4)))
next_transition_counter = transition_counter + 1;
else
next_state = UNSYNCHRONIZED;
@@ -59,13 +59,13 @@ module coax_rx_bit_timer(
else
next_bit_counter = 0;
if (rx != previous_rx && transition_counter > CLOCKS_PER_BIT / 2)
if (rx != previous_rx && transition_counter > (CLOCKS_PER_BIT / 2))
begin
next_transition_counter = 0;
next_bit_counter = CLOCKS_PER_BIT / 2;
end
if (bit_counter == CLOCKS_PER_BIT * 0.75)
if (bit_counter == ((CLOCKS_PER_BIT / 4) * 3))
sample = 1;
end
@@ -76,7 +76,7 @@ module coax_rx_bit_timer(
else
next_bit_counter = 0;
if (bit_counter == CLOCKS_PER_BIT * 0.75)
if (bit_counter == ((CLOCKS_PER_BIT / 4) * 3))
sample = 1;
end
endcase

26
interface2/rtl/top.v
View File

@@ -3,6 +3,13 @@
module top (
input clk_16mhz,
// Receiver
input rx,
input reset,
output sample,
output synchronized,
output usb_pu
);
// 19 MHz
@@ -23,5 +30,24 @@ module top (
.PLLOUTCORE(clk_19mhz)
);
reg rx_0 = 0;
reg rx_1 = 1;
always @(posedge clk_19mhz)
begin
rx_0 <= rx;
rx_1 <= rx_0;
end
coax_rx_bit_timer #(
.CLOCKS_PER_BIT(8)
) rx_bit_timer (
.clk(clk_19mhz),
.rx(rx_1),
.reset(reset),
.sample(sample),
.synchronized(synchronized)
);
assign usb_pu = 0;
endmodule

832
interface2/tests/coax_rx_bit_timer_tb.vcd_snapshot Normal file
View File

@@ -0,0 +1,832 @@
$date
Mon Jun 15 21:59:45 2020
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module coax_rx_bit_timer_tb $end
$var wire 1 ! synchronized $end
$var wire 1 " sample $end
$var reg 1 # clk $end
$var reg 1 $ reset $end
$var reg 1 % rx $end
$scope module dut $end
$var wire 1 # clk $end
$var wire 1 $ reset $end
$var wire 1 % rx $end
$var reg 4 & bit_counter [3:0] $end
$var reg 4 ' next_bit_counter [3:0] $end
$var reg 2 ( next_state [1:0] $end
$var reg 5 ) next_transition_counter [4:0] $end
$var reg 1 * previous_rx $end
$var reg 1 " sample $end
$var reg 2 + state [1:0] $end
$var reg 1 ! synchronized $end
$var reg 5 , transition_counter [4:0] $end
$upscope $end
$scope task rx_bit $end
$var reg 1 - bit $end
$upscope $end
$scope task rx_bit_custom $end
$var reg 1 . bit $end
$var reg 16 / first_half_duration [15:0] $end
$var reg 16 0 second_half_duration [15:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
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