mirror of
https://github.com/lowobservable/coax.git
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72 lines
2.0 KiB
Plaintext
72 lines
2.0 KiB
Plaintext
#-- Synopsys, Inc.
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#-- Project file /home/andrew/lattice_coax/coax/coax_syn.prj
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#project files
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add_file -verilog -lib work "coax_buffered_rx.v"
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add_file -verilog -lib work "coax_rx.v"
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add_file -verilog -lib work "coax_rx_bit_timer.v"
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add_file -verilog -lib work "coax_tx.v"
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add_file -verilog -lib work "coax_tx_bit_timer.v"
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add_file -verilog -lib work "coax_tx_distorter.v"
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add_file -verilog -lib work "control.v"
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add_file -verilog -lib work "spi_device.v"
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add_file -verilog -lib work "coax_buffered_tx.v"
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add_file -verilog -lib work "coax_buffer.v"
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add_file -verilog -lib work "third_party/fifo_sync_ram.v"
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add_file -verilog -lib work "third_party/ram_sdp.v"
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add_file -verilog -lib work "strobe_cdc.v"
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add_file -verilog -lib work "top.v"
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add_file -verilog -lib work "dual_clock_spi_device.v"
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add_file -constraint -lib work "clocks.sdc"
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#implementation: "coax_Implmnt"
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impl -add coax_Implmnt -type fpga
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#implementation attributes
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set_option -vlog_std v2001
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set_option -project_relative_includes 1
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#device options
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set_option -technology SBTiCE40UP
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set_option -part iCE40UP5K
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set_option -package SG48
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set_option -speed_grade
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set_option -part_companion ""
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#compilation/mapping options
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# mapper_options
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set_option -frequency auto
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set_option -write_verilog 0
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set_option -write_vhdl 0
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# Silicon Blue iCE40UP
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set_option -maxfan 10000
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set_option -disable_io_insertion 0
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set_option -pipe 1
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set_option -retiming 0
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set_option -update_models_cp 0
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set_option -fixgatedclocks 2
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set_option -fixgeneratedclocks 0
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# NFilter
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set_option -popfeed 0
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set_option -constprop 0
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set_option -createhierarchy 0
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# sequential_optimization_options
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set_option -symbolic_fsm_compiler 1
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# Compiler Options
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set_option -compiler_compatible 0
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set_option -resource_sharing 1
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#automatic place and route (vendor) options
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set_option -write_apr_constraint 1
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#set result format/file last
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project -result_format "edif"
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project -result_file ./coax_Implmnt/coax.edf
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project -log_file "./coax_Implmnt/coax.srr"
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impl -active coax_Implmnt
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project -run synthesis -clean
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