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sim: sim_halfword: handle HRRE/HRREI/HRREM/HRRES, add unit tests

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This commit is contained in:
Mikael Pettersson
2020-07-27 21:16:16 +02:00
parent 757e25e922
commit 44ceaf1409
3 changed files with 117 additions and 0 deletions
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4
erlang/apps/sim/src/sim_core.erl
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@@ -361,6 +361,10 @@ dispatch(Core, Mem, IR, EA) ->
8#561 -> sim_halfword:handle_HRROI(Core, Mem, IR, EA);
8#562 -> sim_halfword:handle_HRROM(Core, Mem, IR, EA);
8#563 -> sim_halfword:handle_HRROS(Core, Mem, IR, EA);
8#570 -> sim_halfword:handle_HRRE(Core, Mem, IR, EA);
8#571 -> sim_halfword:handle_HRREI(Core, Mem, IR, EA);
8#572 -> sim_halfword:handle_HRREM(Core, Mem, IR, EA);
8#573 -> sim_halfword:handle_HRRES(Core, Mem, IR, EA);
_ ->
PC = (Core#core.pc_section bsl 18) bor Core#core.pc_offset,
{Core, Mem, {error, {?MODULE, {dispatch, PC, IR, EA}}}}

51
erlang/apps/sim/src/sim_halfword.erl
View File

@@ -54,6 +54,10 @@
, handle_HRLZM/4
, handle_HRLZS/4
, handle_HRR/4
, handle_HRRE/4
, handle_HRREI/4
, handle_HRREM/4
, handle_HRRES/4
, handle_HRRI/4
, handle_HRRM/4
, handle_HRRO/4
@@ -547,6 +551,49 @@ handle_HRROS(Core, Mem, IR, EA) ->
fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
end.
%% HRRE - Half Word Right to Right, Extend
-spec handle_HRRE(#core{}, sim_mem:mem(), IR :: word(), #ea{})
-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
handle_HRRE(Core, Mem, IR, EA) ->
case sim_core:c(Core, Mem, EA) of
{ok, CE} ->
AC = IR band 8#17,
Word = set_right_extend(get_right(CE)),
sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem);
{error, Reason} ->
sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
end.
-spec handle_HRREI(#core{}, sim_mem:mem(), IR :: word(), #ea{})
-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
handle_HRREI(Core, Mem, IR, EA) ->
AC = IR band 8#17,
Word = set_right_extend(EA#ea.offset),
sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem).
-spec handle_HRREM(#core{}, sim_mem:mem(), IR :: word(), #ea{})
-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
handle_HRREM(Core, Mem, IR, EA) ->
AC = IR band 8#17,
CA = sim_core:get_ac(Core, AC),
Word = set_right_extend(get_right(CA)),
handle_writeback(Core, Mem, EA, Word).
-spec handle_HRRES(#core{}, sim_mem:mem(), IR :: word(), #ea{})
-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
handle_HRRES(Core, Mem, IR, EA) ->
case sim_core:c(Core, Mem, EA) of
{ok, CE} ->
AC = IR band 8#17,
Word = set_right_extend(get_right(CE)),
handle_writeback(Core, Mem, AC, EA, Word);
{error, Reason} ->
sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
end.
%% Miscellaneous ===============================================================
handle_writeback(Core, Mem, EA, Word) ->
@@ -588,3 +635,7 @@ set_left_zeros(Left) -> Left bsl 18.
set_right(Word, Right) -> (Word band (((1 bsl 18) - 1) bsl 18)) bor Right.
set_right_ones(Right) -> (((1 bsl 18) - 1) bsl 18) bor Right.
set_right_extend(Right) ->
UInt18Sbit = 1 bsl (18 - 1),
((Right bxor UInt18Sbit) - UInt18Sbit) band ((1 bsl 36) - 1).