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sim: sim_halfword: handle HLRE/HLREM/HLRES, sim_core: handle HLREI as SETZ, add unit tests
This commit is contained in:
Mikael Pettersson
parent
d28fe0836f
commit
8ff6957f20
@ -377,6 +377,10 @@ dispatch(Core, Mem, IR, EA) ->
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8#571 -> sim_halfword:handle_HRREI(Core, Mem, IR, EA);
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8#572 -> sim_halfword:handle_HRREM(Core, Mem, IR, EA);
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8#573 -> sim_halfword:handle_HRRES(Core, Mem, IR, EA);
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8#574 -> sim_halfword:handle_HLRE(Core, Mem, IR, EA);
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8#575 -> sim_boolean:handle_SETZ(Core, Mem, IR, EA); % HLREI = HLRZI = SETZ
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8#576 -> sim_halfword:handle_HLREM(Core, Mem, IR, EA);
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8#577 -> sim_halfword:handle_HLRES(Core, Mem, IR, EA);
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_ ->
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PC = (Core#core.pc_section bsl 18) bor Core#core.pc_offset,
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{Core, Mem, {error, {?MODULE, {dispatch, PC, IR, EA}}}}
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@ -39,6 +39,9 @@
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, handle_HLLZM/4
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, handle_HLLZS/4
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, handle_HLR/4
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, handle_HLRE/4
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, handle_HLREM/4
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, handle_HLRES/4
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, handle_HLRI/4
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, handle_HLRM/4
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, handle_HLRO/4
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@ -735,6 +738,42 @@ handle_HLROS(Core, Mem, IR, EA) ->
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fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
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end.
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%% HLRE - Half Word Left to Right, Extend
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-spec handle_HLRE(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HLRE(Core, Mem, IR, EA) ->
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case sim_core:c(Core, Mem, EA) of
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{ok, CE} ->
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AC = IR band 8#17,
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Word = set_right_extend(get_left(CE)),
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sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem);
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{error, Reason} ->
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sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
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fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
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end.
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-spec handle_HLREM(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HLREM(Core, Mem, IR, EA) ->
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AC = IR band 8#17,
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CA = sim_core:get_ac(Core, AC),
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Word = set_right_extend(get_left(CA)),
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handle_writeback(Core, Mem, EA, Word).
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-spec handle_HLRES(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HLRES(Core, Mem, IR, EA) ->
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case sim_core:c(Core, Mem, EA) of
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{ok, CE} ->
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AC = IR band 8#17,
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Word = set_right_extend(get_left(CE)),
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handle_writeback(Core, Mem, AC, EA, Word);
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{error, Reason} ->
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sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
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fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
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end.
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%% Miscellaneous ===============================================================
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handle_writeback(Core, Mem, EA, Word) ->
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@ -105,6 +105,10 @@
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-define(OP_HRREI, 8#571).
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-define(OP_HRREM, 8#572).
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-define(OP_HRRES, 8#573).
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-define(OP_HLRE, 8#574).
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-define(OP_HLREI, 8#575).
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-define(OP_HLREM, 8#576).
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-define(OP_HLRES, 8#577).
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%% 2.8 Half-Word Data Transmission =============================================
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@ -999,6 +1003,64 @@ hlros_no_ac_test() ->
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, {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(1, 0)} % AC0 = 1,,1
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]).
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%% HLRE - Half Word Left to Right, Extend
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hlre_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 1,,100/ MOVEI 1,1
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, {1, 8#101, ?INSN(?OP_HLRE, 1, 0, 0, 8#200)} % 1,,101/ HLRE 1,200
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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, {1, 8#200, ?COMMA2(8#400000, 0)} % 1,,200/ 400000,,0
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(-1, 8#400000)} % AC1 = -1,,400000
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]).
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hlrei_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 1,,100/ MOVEI 1,1
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, {1, 8#101, ?INSN(?OP_HLREI, 1, 0, 0, 1)} % 1,,101/ HLREI 1,1
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(0, 0)} % AC1 = 0,,0
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]).
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hlrem_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVSI, 1, 0, 0, 1)} % 1,,100/ MOVSI 1,1
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, {1, 8#101, ?INSN(?OP_HLREM, 1, 0, 0, 8#200)} % 1,,101/ HLREM 1,200
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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, {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(0, 1)} % C(1,,200) = 0,,1
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]).
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hlres_ac_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVEI, 1, 0, 0, 1)} % 1,,100/ MOVEI 1,1
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, {1, 8#101, ?INSN(?OP_HLRES, 1, 0, 0, 8#200)} % 1,,101/ HLRES 1,200
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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, {1, 8#200, ?COMMA2(8#400000, 0)} % 1,,200/ 400000,,0
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(-1, 8#400000)} % C(1,,200) = -1,,400000
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, {#ea{section = 1, offset = 1, islocal = false}, ?COMMA2(-1, 8#400000)} % AC1 = -1,,400000
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]).
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hlres_no_ac_test() ->
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Prog =
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[ {1, 8#100, ?INSN(?OP_MOVSI, 0, 0, 0, 1)} % 1,,100/ MOVSI 0,1
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, {1, 8#101, ?INSN(?OP_HLRES, 0, 0, 0, 8#200)} % 1,,101/ HLRES 0,200
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, {1, 8#102, ?INSN_INVALID} % 1,,102/ <invalid>
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, {1, 8#200, ?COMMA2(1, 0)} % 1,,200/ 1,,0
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],
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expect(Prog, [], {1, 8#102}, ?DEFAULT_FLAGS,
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[ {#ea{section = 1, offset = 8#200, islocal = false}, ?COMMA2(0, 1)} % C(1,,200) = 0,,1
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, {#ea{section = 1, offset = 0, islocal = false}, ?COMMA2(1, 0)} % AC0 = 1,,0
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]).
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%% Common code to run short sequences ==========================================
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expect(Prog, ACs, ExpectedPC, ExpectedFlags, ExpectedEs) ->
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