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sim: sim_halfword: handle HLRE/HLREM/HLRES, sim_core: handle HLREI as SETZ, add unit tests

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This commit is contained in:
Mikael Pettersson
2020-07-28 00:15:32 +02:00
parent d28fe0836f
commit 8ff6957f20
3 changed files with 105 additions and 0 deletions
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4
erlang/apps/sim/src/sim_core.erl
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@@ -377,6 +377,10 @@ dispatch(Core, Mem, IR, EA) ->
8#571 -> sim_halfword:handle_HRREI(Core, Mem, IR, EA);
8#572 -> sim_halfword:handle_HRREM(Core, Mem, IR, EA);
8#573 -> sim_halfword:handle_HRRES(Core, Mem, IR, EA);
8#574 -> sim_halfword:handle_HLRE(Core, Mem, IR, EA);
8#575 -> sim_boolean:handle_SETZ(Core, Mem, IR, EA); % HLREI = HLRZI = SETZ
8#576 -> sim_halfword:handle_HLREM(Core, Mem, IR, EA);
8#577 -> sim_halfword:handle_HLRES(Core, Mem, IR, EA);
_ ->
PC = (Core#core.pc_section bsl 18) bor Core#core.pc_offset,
{Core, Mem, {error, {?MODULE, {dispatch, PC, IR, EA}}}}

39
erlang/apps/sim/src/sim_halfword.erl
View File

@@ -39,6 +39,9 @@
, handle_HLLZM/4
, handle_HLLZS/4
, handle_HLR/4
, handle_HLRE/4
, handle_HLREM/4
, handle_HLRES/4
, handle_HLRI/4
, handle_HLRM/4
, handle_HLRO/4
@@ -735,6 +738,42 @@ handle_HLROS(Core, Mem, IR, EA) ->
fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
end.
%% HLRE - Half Word Left to Right, Extend
-spec handle_HLRE(#core{}, sim_mem:mem(), IR :: word(), #ea{})
-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
handle_HLRE(Core, Mem, IR, EA) ->
case sim_core:c(Core, Mem, EA) of
{ok, CE} ->
AC = IR band 8#17,
Word = set_right_extend(get_left(CE)),
sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem);
{error, Reason} ->
sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
end.
-spec handle_HLREM(#core{}, sim_mem:mem(), IR :: word(), #ea{})
-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
handle_HLREM(Core, Mem, IR, EA) ->
AC = IR band 8#17,
CA = sim_core:get_ac(Core, AC),
Word = set_right_extend(get_left(CA)),
handle_writeback(Core, Mem, EA, Word).
-spec handle_HLRES(#core{}, sim_mem:mem(), IR :: word(), #ea{})
-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
handle_HLRES(Core, Mem, IR, EA) ->
case sim_core:c(Core, Mem, EA) of
{ok, CE} ->
AC = IR band 8#17,
Word = set_right_extend(get_left(CE)),
handle_writeback(Core, Mem, AC, EA, Word);
{error, Reason} ->
sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
end.
%% Miscellaneous ===============================================================
handle_writeback(Core, Mem, EA, Word) ->